MC68HC812A4CPV8 Motorola, MC68HC812A4CPV8 Datasheet
MC68HC812A4CPV8
Specifications of MC68HC812A4CPV8
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MC68HC812A4CPV8 Summary of contents
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... Table 6 ATD DC Electrical Characteristics Table 7 Analog Converter Characteristics (Operating) Table 8 ATD AC Characteristics (Operating) Table 9 EEPROM Characteristics Table 10 Control Timing Table 11 Peripheral Port Timing Table 12 Non-Multiplexed Expansion Bus Timing Table 13 SPI Timing PRELIMINARY © MOTOROLA INC, 1997, 1998 Order this document by 7/28/98 MC68HC812A4EC/D ...
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... Device internal power dissipation 2 I/O pin power dissipation 3 A constant NOTES: 1. This is an approximate value, neglecting P 2. For most applications P « constant pertaining to the device. Solve for K with a known T this value solve for P D MOTOROLA 2 Table 1 Maximum Ratings Table 2 Thermal Characteristics Symbol ...
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... Symbol , XIRQ, reduced drive strength FP Min Max Unit 0.3 0 0.2 — 0.8 — 0.2 — 0.8 — — — — — — — — 2 — — — — — 130 500 A APU V 2.0 — — MOTOROLA 3 ...
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... EXTAL DD Characteristic ATD reference voltage DDA SSA V differential voltage SS V differential voltage DD V differential voltage REF Reference to supply differential voltage MOTOROLA 4 Table 4 Supply Current 0 Vdc unless otherwise noted Symbol Single-chip mode I DD Expanded mode Single-chip mode W IDD Expanded mode S IDD ...
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... Vdc ATD Clock otherwise noted Symbol V DDA Normal operation I DDA INDC I OFF I REF Not Sampling C INN Sampling C INS 3.3 Vdc 0. SSA RL INDC 2 MHz, unless Min Max Unit 3.0 3 SSA DDA DDA DDA 3.0 3 SSA DDA 100 nA 250 DDA MOTOROLA 5 ...
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... V ERRJ Table 8 ATD AC Characteristics (Operating) V 3.3 Vdc 0.3V Characteristic ATD operating clock frequency Conversion time per channel 0.5 MHz f ATDCLK 18 ATD clocks 32 ATD clocks Stop recovery time V MOTOROLA 6 0 Vdc ATD Clock Symbol 2 counts DNL INL ERRJ V ...
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... MHz o t 200 — ns cyc f — 10.0 MHz XTAL 2f dc 10.0 MHz o t 130 — ns PCSU PW 32 — t RSTL cyc 2 — t cyc t 4 — t MPS cyc t 10 — ns MPH PW 420 — ns IRQ t — WRS cyc PW 420 — ns TIM MOTOROLA Unit ...
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... PT[7:0] PW TIM 2 PT[7:0] 1 PT7 PT7 NOTES : 1. Rising edge sensitive input 2. Falling edge sensitive input MOTOROLA 8 Figure 1 Timer Inputs TIMER INPUT TIMING MC68C812A4 ...
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... Figure 2 POR and External Reset Timing Diagram MC68C812A4 MOTOROLA 9 ...
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... Figure 3 STOP Recovery Timing Diagram MOTOROLA 10 STOP RECOVERY TIM MC68C812A4 ...
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... Figure 4 WAIT Recovery Timing Diagram MC68C812A4 WAIT RECOVERY TIM MOTOROLA 11 ...
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... MOTOROLA 12 Figure 5 Interrupt Timing Diagram INTERRUPT TIM MC68C812A4 ...
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... Figure 6 Port Read Timing Diagram MCU WRITE TO PORT PREVIOUS PORT DATA Figure 7 Port Write Timing Diagram 5.0 MHz Unit Min Max f dc 5.0 MHz o 200 — ns cyc 130 — — ns — PDH PORT RD TIM t PWD NEW DATA VALID PORT WR TIM MOTOROLA 13 ...
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... Chip select access time 27 28 Chip select hold time 29 Chip select negated time NOTES: 1. All timings are calculated for normal port drives. 2. This characteristic is affected by clock stretch. Add N t where depending on the number of clock stretches. cyc MOTOROLA 14 0.3V Vdc unless otherwise noted Delay Symbol ...
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... ECLK 5 ADDR[15:0] DATA[15:0] READ DATA[15:0] WRITE 16 R/W 19 LSTRB (W/O TAG ENABLED NOTE: Measurement points shown are 20% and 70 Figure 8 Non-Multiplexed Expansion Bus Timing Diagram MC68C812A4 BUS TIM MOTOROLA 15 ...
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... Data Valid (after SCK Edge) 10 Master Slave Data Hold Time (Outputs) 11 Master Slave Rise Time 12 Input Output Fall Time 13 Input Output NOTES: 1. All AC timing is shown with respect to 20% V MOTOROLA 16 Table 13 SPI Timing , V 0 Vdc 130 pF load on all SPI pins Symbol Min ...
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... LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. MC68C812A4 1 4 BIT 6 1 LSB BIT SPI Master Timing (CPHA = BIT BIT 6 1 MASTER LSB OUT . . . B) SPI Master Timing (CPHA = 1) Figure 9 SPI Timing Diagram ( LSB OUT SPI MASTER CPHA0 5 3 LSB IN PORT DATA SPI MASTER CPHA1 MOTOROLA 17 ...
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... SCK (CPOL 1) (INPUT) 10 MISO SEE SLAVE MSB OUT (OUTPUT) NOTE MOSI MSB IN (INPUT) NOTE: Not defined but normally LSB of character just received. Figure 10 SPI Timing Diagram ( MOTOROLA BIT 6 1 SLAVE LSB OUT . . . BIT 6 1 LSB SPI Slave Timing (CPHA ...