HD6417750 Renesas Electronics Corporation., HD6417750 Datasheet
HD6417750
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HD6417750 Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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Hitachi SuperH SH7750, SH7750S, SH7750R ADE-602-124E Rev. 6.0 7/10/2002 Hitachi, Ltd. RISC engine SH7750 Series Hardware Manual ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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The SH-4 (SH7750 Series: SH7750, SH7750S, SH7750R) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7750 Series is built in with a variety of peripheral functions such as ...
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User manuals for development tools Name of Document C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual Simulator/Debugger User’s Manual Hitachi Embedded Workshop User’s Manual Rev. 6.0, 07/02, page Document No. ADE-702-246 ADE-702-186 ADE-702-201 ...
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List of Items Revised or Added for This Version Section 1.1 SH7750 Series (SH7750, SH7750S, SH7750R) Features 1.2 Block Diagram 1.3 Pin Arrangement 1.4 Pin Functions 2.7 Processor Modes 3.2 Register Descriptions 3.3.1 Physical Address Space Page Item 1 4 ...
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Section 3.3.3 Virtual Address Space 3.3.4 On-Chip RAM Space 3.3.7 Address Space Identifier (ASID) 4.1.1 Features 4.2 Register Descriptions 4.3.1 Configuration 4.3.6 RAM Mode 4.3.7 OC Index Mode 4.4.1 Configuration 4.6 Memory-Mapped Cache Configuration (SH7750R) 4.7 Store Queues 4.7.3 Transfer ...
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Section 5.6.3 Interrupts 7.3 Instruction Set 8.3 Execution Cycles and Pipeline Stalling 9.1.1 Types of Power-Down Modes 9.1.2 Register Configuration 9.1.3 Pin Configuration 9.2.2 Peripheral Module Pin High Impedance Control 9.2.3 Peripheral Module Pin Pull-Up Control 9.2.4 Standby Control Register ...
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Section 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) 10.2.1 Block Diagram of CPG 10.2.2 CPG Pin Configuration 10.2.3 CPG Register Configuration 10.3 Clock Operating Modes 10.8.2 Watchdog Timer Control/Status Register (WTCSR) 10.10 Notes on Board Design 11.1.1 Features 11.1.2 ...
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Section 11.2.2 Second Counter (RSECCNT) 11.2.17 RTC Control Register 3 (RCR3) and Year- Alarm Register (RYRAR) (SH7750R Only) 11.3.3 Alarm Function 11.5.2 Carry Flag and Interrupt Flag in Standby Mode 11.5.3 Crystal Oscillator Circuit 12.1.1 Features 12.1.2 Block Diagram 12.1.4 ...
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Section 13.1.4 Register Configuration 318 13.1.5 Overview of Areas 13.2.1 Bus Control Register 1 (BCR1) 13.2.2 Bus Control Register 2 (BCR2) 13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only) 13.2.4 Bus Control Register 4 (BCR4) 13.2.5 Wait Control Register 1 ...
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Section 13.2.8 Memory Control Register (MCR) 13.2.10 Synchronous DRAM Mode Register (SDMR) 13.3.1 Endian/Access Size and Data Alignment 13.3.2 Areas 13.3.3 SRAM Interface 13.3.4 DRAM Interface 13.3.5 Synchronous DRAM Interface 13.3.6 Burst ROM Interface Page Item 355 Bits 15 to ...
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Section 13.3.7 PCMCIA Interface 13.3.8 MPX Interface 13.3.9 Byte Control SRAM Interface 13.3.10 Waits between Access Cycles 13.3.11 Bus Arbitration 13.3.16 Notes on Usage 14.1 Overview 14.1.1 Features 14.1.2 Block Diagram (SH7750, SH7750S) 14.2 Register Descriptions (SH7750, SH7750S) Rev. 6.0, ...
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Section 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0– DMATCR3) 14.2.4 DMA Channel Control Registers 0–3 (CHCR0– CHCR3) 14.2.5 DMA Operation Register (DMAOR) 14.3.2 DMA Transfer Requests ...
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Section 14.6 Configuration of the DMAC (SH7750R) 14.7 Register Descriptions (SH7750R) 14.8 Operation (SH7750R) 14.9 Usage Notes 15.2.8 Serial Port Register (SCSPTR1) 16.1.2 Block Diagram 16.1.3 Pin Configuration 16.2.6 Serial Control Register (SCSCR2) 16.2.7 Serial Status Register (SCFSR2) 16.2.9 FIFO ...
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Section 19.2.4 Interrupt Exception Handling and Priority 19.3.1 Interrupt Priority Registers (IPRA– IPRD) 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only) 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) 19.3.6 Interrupt ...
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... Table 22.4 DC Characteristics (HD6417750RBP200) 820, 821 Table 22.5 DC Characteristics (HD6417750RF200) 822, 823 Table 22.6 DC Characteristics (HD6417750SBP200) 826, 827 Table 22.8 DC Characteristics (HD6417750BP200M) Description Table amended and Note 3 added Description added to table and Notes 3 and 4 added [SH7750R] description added ...
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... Table 22.22 Clock Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I) 843 Table 22.23 Clock Timing (HD6417750SVF133, HD6417750SVBT133) 843 Table 22.24 Clock Timing (HD6417750VF128) 844, 845 Table 22.25 Clock and Control Signal Timing (HD6417750RBP240) 846, 847 Table 22.26 Clock and Control Signal Timing ...
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... Table 22.30 Clock and Control Signal Timing (HD6417750SF200) 856, 857 Table 22.31 Clock and Control Signal Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I) 858, 859 Table 22.32 Clock and Control Signal Timing (HD6417750SVF133, HD6417750SVBT133) 860, 861 Table 22.33 Clock and Control Signal Timing ...
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Section 22.3.4 Peripheral Module Signal Timing Appendix A Address List Appendix B Package Dimensions Appendix C Mode Pin Settings Appendix D &.,25(1% Pin Configuration Appendix E Pin Functions Appendix F Synchronous DRAM Address Multiplexing Tables Page Item 924, 925 Table ...
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Section Appendix F Synchronous DRAM Address Multiplexing Tables Appendix H Power-On and Power-Off Procedures Appendix I Product Code Lineup Rev. 6.0, 07/02, page Page Item 972, 973 (19) BUS 32 (128M: 4M × 8b × 4) × ...
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Section 1 Overview ........................................................................................................... 1.1 SH7750 Series (SH7750, SH7750S, SH7750R) Features ................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Arrangement ............................................................................................................... 10 1.4 Pin Functions..................................................................................................................... 13 1.4.1 Pin Functions (256-Pin BGA) .............................................................................. 13 1.4.2 Pin Functions (208-Pin QFP) ............................................................................... 23 1.4.3 ...
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Unified TLB (UTLB) Configuration.................................................................... 71 3.4.2 Instruction TLB (ITLB) Configuration ................................................................ 75 3.4.3 Address Translation Method ................................................................................ 75 3.5 MMU Functions ................................................................................................................ 78 3.5.1 MMU Hardware Management ............................................................................. 78 3.5.2 MMU Software Management............................................................................... 78 3.5.3 MMU Instruction (LDTLB) ................................................................................. ...
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IC Index Mode ..................................................................................................... 111 4.5 Memory-Mapped Cache Configuration (SH7750, SH7750S)........................................... 112 4.5.1 IC Address Array ................................................................................................. 112 4.5.2 IC Data Array ....................................................................................................... 113 4.5.3 OC Address Array................................................................................................ 114 4.5.4 OC Data Array ..................................................................................................... 115 4.6 Memory-Mapped Cache Configuration ...
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Section 6 Floating-Point Unit 6.1 Overview ........................................................................................................................... 161 6.2 Data Formats ..................................................................................................................... 161 6.2.1 Floating-Point Format .......................................................................................... 161 6.2.2 Non-Numbers (NaN)............................................................................................ 163 6.2.3 Denormalized Numbers........................................................................................ 164 6.3 Registers ............................................................................................................................ 165 6.3.1 Floating-Point Registers ....................................................................................... 165 6.3.2 Floating-Point Status/Control Register (FPSCR) ...
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Exit from Deep Sleep Mode................................................................................. 231 9.5 Standby Mode ................................................................................................................... 231 9.5.1 Transition to Standby Mode................................................................................. 231 9.5.2 Exit from Standby Mode ...................................................................................... 232 9.5.3 Clock Pause Function........................................................................................... 232 9.6 Module Standby Function ................................................................................................. 233 9.6.1 Transition to Module ...
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Using the WDT ................................................................................................................. 263 10.9.1 Standby Clearing Procedure................................................................................. 263 10.9.2 Frequency Changing Procedure ........................................................................... 264 10.9.3 Using Watchdog Timer Mode.............................................................................. 264 10.9.4 Using Interval Timer Mode.................................................................................. 265 10.10 Notes on Board Design...................................................................................................... 265 Section 11 Realtime Clock (RTC) ...
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Section 12 Timer Unit (TMU) 12.1 Overview ........................................................................................................................... 291 12.1.1 Features ................................................................................................................ 291 12.1.2 Block Diagram ..................................................................................................... 292 12.1.3 Pin Configuration ................................................................................................. 292 12.1.4 Register Configuration ......................................................................................... 293 12.2 Register Descriptions ........................................................................................................ 295 12.2.1 Timer Output Control Register (TOCR) .............................................................. ...
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Refresh Timer Control/Status Register (RTCSR) ................................................ 364 13.2.12 Refresh Timer Counter (RTCNT) ........................................................................ 367 13.2.13 Refresh Time Constant Register (RTCOR).......................................................... 368 13.2.14 Refresh Count Register (RFCR)........................................................................... 369 13.2.15 Notes on Accessing Refresh Control Registers.................................................... 369 13.3 Operation........................................................................................................................... 370 13.3.1 ...
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Examples of Transfer between External Memory and an External Device with DACK .......................................................................................................... 544 14.5 On-Demand Data Transfer Mode (DDT Mode)................................................................ 545 14.5.1 Operation.............................................................................................................. 545 14.5.2 Pins in DDT Mode ............................................................................................... 547 14.5.3 Transfer Request Acceptance on Each Channel................................................... ...
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Operation in Asynchronous Mode ....................................................................... 623 15.3.3 Multiprocessor Communication Function............................................................ 634 15.3.4 Operation in Synchronous Mode.......................................................................... 642 15.4 SCI Interrupt Sources and DMAC .................................................................................... 651 15.5 Usage Notes....................................................................................................................... 652 Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview ...
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Overview .............................................................................................................. 710 17.3.2 Pin Connections ................................................................................................... 711 17.3.3 Data Format.......................................................................................................... 712 17.3.4 Register Settings................................................................................................... 713 17.3.5 Clock .................................................................................................................... 715 17.3.6 Data Transmit/Receive Operations....................................................................... 718 17.4 Usage Notes....................................................................................................................... 725 Section 18 I/O Ports ............................................................................................................ 731 18.1 Overview ........................................................................................................................... 731 ...
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INTC Operation................................................................................................................. 768 19.4.1 Interrupt Operation Sequence............................................................................... 768 19.4.2 Multiple Interrupts................................................................................................ 770 19.4.3 Interrupt Masking with MAI Bit .......................................................................... 770 19.5 Interrupt Response Time ................................................................................................... 771 Section 20 User Break Controller (UBC) 20.1 Overview ........................................................................................................................... 773 20.1.1 Features ................................................................................................................ ...
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Block Diagram ..................................................................................................... 799 21.1.3 Pin Configuration ................................................................................................. 801 21.1.4 Register Configuration ......................................................................................... 802 21.2 Register Descriptions ........................................................................................................ 803 21.2.1 Instruction Register (SDIR).................................................................................. 803 21.2.2 Data Register (SDDR).......................................................................................... 805 21.2.3 Bypass Register (SDBPR).................................................................................... 805 21.2.4 Interrupt Source Register (SDINT) ...
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Appendix H Power-On and Power-Off Procedures Appendix I Product Code Lineup Index ........................................................................................................................................... 981 Figures Figure 1.1 Block Diagram of SH7750 Series Functions.................................................... Figure 1.2 Pin Arrangement (256-Pin BGA)..................................................................... 10 Figure 1.3 Pin Arrangement (208-Pin QFP) ...................................................................... 11 Figure 1.4 ...
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Figure 4.8 Memory-Mapped IC Address Array ................................................................ 113 Figure 4.9 Memory-Mapped IC Data Array ...................................................................... 114 Figure 4.10 Memory-Mapped OC Address Array............................................................... 115 Figure 4.11 Memory-Mapped OC Data Array .................................................................... 116 Figure 4.12 Memory-Mapped IC Address Array ................................................................ 118 Figure ...
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Figure 11.4 Example of Use of Alarm Function.................................................................. 288 Figure 11.5 Example of Crystal Oscillator Circuit Connection........................................... 290 Figure 12.1 Block Diagram of TMU ................................................................................... 292 Figure 12.2 Example of Count Operation Setting Procedure .............................................. 305 Figure 12.3 TCNT Auto-Reload ...
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Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) .... 414 Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .... 415 Figure 13.28 Basic Timing for Synchronous DRAM Burst Read ......................................... 417 Figure ...
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Figure 13.61 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 461 Figure 13.62 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait ...
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Figure 14.1 Block Diagram of DMAC ................................................................................ 492 Figure 14.2 DMAC Transfer Flowchart .............................................................................. 511 Figure 14.3 Round Robin Mode .......................................................................................... 516 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode......................... 517 Figure 14.5 Data Flow in ...
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Figure 14.28 Dual Address Mode/Synchronous DRAM Figure 14.29 Single Address Mode/Burst Mode/External Bus Block Transfer/Channel 0 On-Demand Data Transfer..................................... 554 Figure 14.30 Single Address Mode/Burst Mode/External Device Block Transfer/Channel 0 On-Demand Data Transfer..................................... 554 Figure 14.31 Single Address Mode/Burst Mode/External ...
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Figure 14.54 DTR Format (Transfer Request Format) (SH7750R)....................................... 584 Figure 14.55 Single Address Mode/Burst Mode/External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ....................... 589 Figure 14.56 Single Address Mode/Burst Mode/External Bus 32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 ...
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Figure 16.4 MD1/TxD2 Pin................................................................................................. 683 Figure 16.5 MD2/RxD2 Pin ................................................................................................ 683 Figure 16.6 Sample SCIF Initialization Flowchart .............................................................. 689 Figure 16.7 Sample Serial Transmission Flowchart ............................................................ 690 Figure 16.8 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop ...
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Figure 21.3 H-UDI Reset..................................................................................................... 811 Figure 22.1 EXTAL Clock Input Timing ............................................................................ 862 Figure 22.2(1) CKIO Clock Output Timing............................................................................. 862 Figure 22.2(2) CKIO Clock Output Timing............................................................................. 862 Figure 22.3 Power-On Oscillation Settling Time ................................................................ 863 Standby Return Oscillation Settling Time ...
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Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD[1:0] = 01, TRWL[2:0] = 010) ........ 892 Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RCD[1:0] = 01, TPC[2:0] ...
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Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 000, TRC[2:0] = 001) ............................................................... 912 Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001, TRC[2:0] = 001) ............................................................... 913 Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] ...
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Figure 22.67 TCK Input Timing............................................................................................ 932 5(6(7 Hold Timing ........................................................................................ 932 Figure 22.68 Figure 22.69 H-UDI Data Transfer Timing........................................................................... 933 Figure 22.70 Pin Break Timing ............................................................................................. 933 Figure 22.71 NMI Input Timing............................................................................................ 933 Figure 22.72 Output Load Circuit ......................................................................................... 934 ...
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Table 7.12 Floating-Point Graphics Acceleration Instructions ............................................ 191 Table 8.1 Instruction Groups.............................................................................................. 200 Table 8.2 Parallel-Executability ......................................................................................... 204 Table 8.3 Execution Cycles................................................................................................ 211 Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes ........................ 222 Table 9.2 Power-Down Mode ...
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Table 14.2 DMAC Pins in DDT Mode ................................................................................ 494 Table 14.3 DMAC Registers ................................................................................................ 494 Table 14.4 Selecting External Request Mode with RS Bits ................................................. 513 Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits .................. 514 Table ...
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... DC Characteristics (HD6417750RBP200)......................................................... 818 Table 22.5 DC Characteristics (HD6417750RF200) ........................................................... 820 Table 22.6 DC Characteristics (HD6417750SBP200) ......................................................... 822 Table 22.7 DC Characteristics (HD6417750SF200)............................................................ 824 Table 22.8 DC Characteristics (HD6417750BP200M) ........................................................ 826 Table 22.9 DC Characteristics (HD6417750SF167)............................................................ 828 Table 22.10 DC Characteristics (HD6417750SF167I)........................................................... 830 Table 22.11 DC Characteristics (HD6417750F167) .............................................................. 832 Table 22.12 DC Characteristics (HD6417750F167I)............................................................. 834 Table 22 ...
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... Table 22.24 Clock Timing (HD6417750VF128) ................................................................... 843 Table 22.25 Clock and Control Signal Timing (HD6417750RBP240).................................. 844 Table 22.26 Clock and Control Signal Timing (HD6417750RF240) .................................... 846 Table 22.27 Clock and Control Signal Timing (HD6417750RBP200).................................. 848 Table 22.28 Clock and Control Signal Timing (HD6417750RF200) .................................... 850 Table 22 ...
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SH7750 Series (SH7750, SH7750S, SH7750R) Features The SH7750 Series (SH7750, SH7750S, SH7750R 32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH- 3 microcomputers. It includes an instruction cache, an operand ...
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Table 1.1 SH7750 Series Features (cont) Item Features CPU Original Hitachi SH architecture 32-bit internal data bus General register file: Sixteen 32-bit general registers (and eight 32-bit shadow registers) Seven 32-bit control registers Four 32-bit system registers RISC-type instruction set ...
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Table 1.1 SH7750 Series Features (cont) Item Features FPU On-chip floating-point coprocessor Supports single-precision (32 bits) and double-precision (64 bits) Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: ...
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Table 1.1 SH7750 Series Features (cont) Item Features Clock pulse Choice of main clock: generator (CPG) SH7750, SH7750S: 1/ times EXTAL SH7750R times EXTAL Clock modes: CPU frequency: 1, 1/2, 1/3, 1/4, ...
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Table 1.1 SH7750 Series Features (cont) Item Features Cache memory Instruction cache (IC) [SH7750, SH7750S] 8 kbytes, direct mapping 256 entries, 32-byte block length Normal mode (8-kbyte cache) Index mode Operand cache (OC) 16 kbytes, direct mapping 512 entries, 32-byte ...
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Table 1.1 SH7750 Series Features (cont) Item Features Interrupt controller Five independent external interrupts: NMI, IRL3 to IRL0 (INTC) 15-level encoded external interrupts: IRL3 to IRL0 On-chip peripheral module interrupts: Priority level can be set for each module User break ...
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Table 1.1 SH7750 Series Features (cont) Item Features Direct memory Physical address DMA controller: access controller SH7750, SH7750S: 4-channel (DMAC) SH7750R: 8-channel Transfer data size: 8, 16, 32 bits bytes Address modes: Single address mode Dual ...
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... V 128 MHz HD6417750VF128 1.95 V 200 MHz HD6417750SBP200 HD6417750SF200 1.8 V 167 MHz HD6417750SF167 HD6417750SF167I 1.5 V 133 MHz HD6417750SVF133 HD6417750SVBT133 264-pin CSP 1.5 V 240 MHz HD6417750RBP240 HD6417750RF240 200 MHz HD6417750RBP200 HD6417750RF200 Package 256-pin BGA 208-pin QFP 256-pin BGA 208-pin QFP 256-pin BGA ...
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Block Diagram Figure 1.1 shows an internal block diagram of the SH7750 Series. (SCIF) BSC: Bus state controller CPG: Clock pulse generator DMAC: Direct memory access controller FPU: Floating-point unit INTC: Interrupt controller ITLB: Instruction TLB (translation lookaside buffer) ...
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Pin Arrangement D47 D32 E D46 D33 F D45 D34 G D44 D35 H D43 D36 J D42 D37 K D41 L D38 D40 M D39 D15 N D0 D14 ...
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D47 11 D32 D46 15 D33 16 D45 17 D34 18 D44 19 D35 D43 23 D36 24 D42 25 D37 26 D41 27 ...
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A VSS-CPG XTAL EXTAL VDD-CPG B C VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK D VSSQ E F VDD D47 VDDQ G D45 VDDQ D46 VSS H VDDQ D43 D44 D35 J VDDQ D38 D42 D41 K D39 D0 ...
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Pin Functions 1.4.1 Pin Functions (256-Pin BGA) Table 1.2 Pin Functions Pin No. No. Pin Name I/O 5'< 5(6 & & & &68 6 ...
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Table 1.2 Pin Functions (cont) Pin No. No. Pin Name I D42 I D37 I VDDQ Power IO VDD (3 VSSQ Power IO GND ( D41 I/O 34 ...
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Table 1.2 Pin Functions (cont) Pin No. No. Pin Name I/O %$&./ %65(4 %5( %6$& I I CKE VDDQ Power IO VDD (3.3 ...
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Table 1.2 Pin Functions (cont) Pin No. No. Pin Name I VDDQ Power IO VDD (3 VSSQ Power IO GND ( W10 Y10 ...
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Table 1.2 Pin Functions (cont) Pin No. No. Pin Name I/O 115 W16 RD/:5 O :(5/&$65/ 116 Y17 O DQM2/ ,&,25' :(6/&$66/ 117 W17 O DQM3/ ,&,2:5 :(9/&$69/ 118 Y18 O DQM6 119 V16 VDDQ Power IO VDD (3.3 V) ...
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Table 1.2 Pin Functions (cont) Pin No. No. Pin Name I/O 142 R20 D29 I/O 143 N18 VDDQ Power IO VDD (3.3 V) 144 N17 VSSQ Power IO GND (0 V) 145 P19 D17 I/O 146 P20 D30 I/O 147 ...
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Table 1.2 Pin Functions (cont) Pin No. No. Pin Name I/O 174 E19 D63 I/O 175 F18 VDDQ Power IO VDD (3.3 V) 176 F17 VSSQ Power IO GND (0 V) 177 E17 VSSQ Power IO GND (0 V) 178 ...
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Table 1.2 Pin Functions (cont) Pin No. No. Pin Name I/O 197 C15 VDDQ Power IO VDD (3.3 V) 198 D15 VSSQ Power IO GND (0 V) 199 B15 MD7/TXD I/O 200 A16 SCK2/ I 05(6(7 201 C14 VDD Power ...
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Table 1.2 Pin Functions (cont) Pin No. No. Pin Name I/O 225 226 A8 STATUS0 O 227 B8 STATUS1 O 228 A7 MD6/ I ,2,649 229 C9 VDDQ Power IO VDD (3.3 V) 230 D9 VSSQ Power ...
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Table 1.2 Pin Functions (cont) Pin No. No. Pin Name I/O 248 A1 EXTAL I 249 C5 NC 250 D16 NC 251 H17 NC 252 H18 NC 253 N3 NC 254 N4 NC 255 U4 NC 256 V18 NC I: ...
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Pin Functions (208-Pin QFP) Table 1.3 Pin Functions Pin No. Pin Name I/O Function 5'< Bus ready 5(6 Reset & Chip select 0 & Chip select 1 & Chip ...
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Table 1.3 Pin Functions (cont) Pin No. Pin Name I/O Function 31 VDDQ Power IO VDD (3 VSSQ Power IO GND ( D15 I/O Data 34 D0 I/O Data 35 D14 I/O Data 36 D1 I/O ...
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Table 1.3 Pin Functions (cont) Pin No. Pin Name I/O Function :(7/&$67 D39–D32 select DQM4 signal :(4/&$64 D15–D8 select DQM1 signal :(3/&$63 D7–D0 select DQM0 signal 62 A17 O Address 63 A16 O Address ...
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Table 1.3 Pin Functions (cont) Pin No. Pin Name I/O Function 88 VSSQ Power IO GND (0 V) & Chip select 3 & Chip select 2 91 VDD Power Internal VDD 92 VSS Power Internal GND ...
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Table 1.3 Pin Functions (cont) Pin No. Pin Name I/O Function 114 VSSQ Power IO GND (0 V) 115 D19 I/O Data 116 D28 I/O Data 117 VDD Power Internal VDD 118 VSS Power Internal GND (0 V) 119 D18 ...
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Table 1.3 Pin Functions (cont) Pin No. Pin Name I/O Function 145 D48 I/O Data/port 146 D63 I/O Data 147 VDDQ Power IO VDD (3.3 V) 148 VSSQ Power IO GND (0 V) 149 MD0/SCK I/O Mode/SCI clock 150 MD1/TXD2 ...
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Table 1.3 Pin Functions (cont) Pin No. Pin Name I/O Function 168 SCK2/ I SCIF clock/ 05(6(7 manual reset 169 VDD Power Internal VDD 170 VSS Power Internal GND (0 V) 171 A18 O Address 172 A19 O Address 173 ...
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Table 1.3 Pin Functions (cont) Pin No. Pin Name I/O Function 194 TDO O Data out (H-UDI) 195 VDD Power Internal VDD 196 VSS Power Internal GND (0 V) 197 TMS I Mode (H-UDI) 198 TCK I Clock (H-UDI) 199 ...
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Pin Functions (264-Pin CSP) Table 1.4 Pin Functions Pin No. No. Pin Name I/O 5'< 5(6 & & & & &69 ...
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Table 1.4 Pin Functions (cont) Pin No. No. Pin Name I VSSQ Power IO GND ( D41 I D38 I D40 I D39 I VDDQ Power IO ...
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Table 1.4 Pin Functions (cont) Pin No. No. Pin Name I/O %5( %6$& I I CKE VDDQ Power IO VDD (3 VSSQ Power ...
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Table 1.4 Pin Functions (cont) Pin No. No. Pin Name I CKIO VDDQ Power IO VDD (3 VSSQ Power IO GND ( CKIO2 O 94 ...
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Table 1.4 Pin Functions (cont) Pin No. No. Pin Name I/O 116 R14 :(9/&$69/ O DQM6 117 U14 VDDQ Power IO VDD (3.3 V) 118 U17 VSSQ Power IO GND (0 V) 119 U15 :(:/&$6:/ O DQM7/5(* 120 U16 D23 ...
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Table 1.4 Pin Functions (cont) Pin No. No. Pin Name I/O 145 K15 D16 I/O 146 K14 D31 I/O 147 K17 VDDQ Power IO VDD (3.3 V) 148 K13 VSSQ Power IO GND (0 V) 149 K16 D55 I/O 150 ...
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Table 1.4 Pin Functions (cont) Pin No. No. Pin Name I/O 176 F16 MD0/SCK I/O 177 C15 MD1/TXD2 I/O 178 E15 MD2/RXD2 I 179 D15 ,5/3 I 180 D17 ,5/4 I ,5/5 181 A17 I ,5/6 182 B17 I 183 ...
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Table 1.4 Pin Functions (cont) Pin No. No. Pin Name I/O 198 D11 VSS Power Internal GND 199 C11 A18 O 200 F12 A19 O 201 B11 VDDQ Power IO VDD (3.3 V) 202 E11 VSSQ Power IO GND (0 ...
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Table 1.4 Pin Functions (cont) Pin No. No. Pin Name I/O $6(%5./ 227 E6 I/O BRKACK 228 A6 TDO O 229 D7 VDD Power Internal VDD 230 B7 VSS Power Internal GND 231 E5 TMS I 232 C6 TCK I ...
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Table 1.4 Pin Functions (cont) Pin No. No. Pin Name I/O 256 M7 NC-13 257 N2 NC-14 258 P2 NC-15 259 P16 NC-16 260 R17 NC-17 261 T4 NC-18 262 T14 NC-19 263 U3 NC-20 264 U4 NC-21 I: Input ...
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Section 2 Programming Model 2.1 Data Formats The data formats handled by the SH7750 Series are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) Single-precision floating-point (32 bits) Double-precision floating-point (64 bits ...
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Register Configuration 2.2.1 Privileged Mode and Banks Processor Modes: The SH7750 Series has two processor modes, user mode and privileged mode. The SH7750 Series normally operates in user mode, and switches to privileged mode when an exception occurs or ...
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Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or ...
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R0 _ BANK0 * BANK0 * BANK0 * BANK0 * BANK0 * BANK0 * BANK0 * BANK0 * R10 R11 R12 R13 ...
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General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH7750 Series has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1– R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0– ...
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SR. (SR. SR. R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 Programming Note: As the user’s R0–R7 ...
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Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and ...
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Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF4 XF1 XF5 XF2 XF6 XF3 XF7 FPSCR. FV0 DR0 FR0 FR1 DR2 FR2 FR3 FV4 DR4 FR4 FR5 DR6 FR6 FR7 FV8 ...
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Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined ...
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Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The ...
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Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001 — Note: —: Reserved. These bits are always read as 0, and should only be written with 0. FR: Floating-point register bank ...
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When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set ...
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Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded into a register. 31 2.5 ...
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Note: The SH7750 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. 2.6 Processor States The ...
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From any state when = 0 and Power-on reset state Bus request Interrupt Bus-released state Bus request Bus request clearance Figure 2.6 Processor State Transitions 2.7 Processor Modes There are two processor modes: user mode and privileged mode. The processor ...
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Rev. 6.0, 07/02, page 56 of 986 ...
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Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH7750 Series can handle 29-bit external memory space from an 8-bit address space identifier and 32-bit logical (virtual) address space. Address translation from virtual address to physical address is ...
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When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. ...
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Physical Process 1 memory Process 1 Process 1 Process 2 Process 3 Figure 3.1 Role of the MMU Virtual memory Process 1 Physical memory (1) Virtual Physical Process 1 memory memory Process 2 Process 3 (3) Rev. 6.0, 07/02, page ...
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Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Name tion Page table entry high PTEH register Page table entry low PTEL register Page table entry PTEA assistance register Translation table base TTB ...
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Register Descriptions There are six MMU-related registers. 1. PTEH 31 2. PTEL — — — 3. PTEA 31 4. TTB 31 5. TEA 31 Virtual address at which MMU exception or address error occurred 6. ...
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Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). ...
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TI: TLB invalidate AT: Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should ...
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URB: UTLB replace boundary. Bits that indicate the UTLB entry boundary at which replacement performed. Valid only when URB > 0. URC: UTLB replace counter. Random counter for indicating the UTLB entry for which replacement is to ...
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H'0000 0000 P0 area Cacheable H'8000 0000 P1 area Cacheable H'A000 0000 P2 area Non-cacheable H'C000 0000 P3 area Cacheable H'E000 0000 P4 area Non-cacheable H'FFFF FFFF Privileged mode Figure 3.3 Physical Address Space (MMUCR. the SH7750, ...
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P4 Area: The P4 area is mapped onto SH7750 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4. H'E000 0000 H'E400 0000 H'F000 0000 H'F100 0000 H'F200 ...
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The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2. The area from H'F400 ...
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Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH7750 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or ...
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Here, access to the PCMCIA interface area by accessing an area of P1, P2 from the CPU is disabled. In addition, the PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, ...
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P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the area, the physical address is uniquely determined without ...
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TLB Functions 3.4.1 Unified TLB (UTLB) Configuration The unified TLB (UTLB called because of its use for the following two purposes translate a virtual address to a physical address in a data access 2. As ...
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Virtual address 31 VPN • 4-kbyte page Virtual address VPN • 64-kbyte page Virtual address VPN • 1-Mbyte page Virtual address VPN Figure 3.8 Relationship between Page Size ...
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SZ: Page size bits Specify the page size. 00: 1-kbyte page 01: 4-kbyte page 10: 64-kbyte page 11: 1-Mbyte page V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared power-on reset. ...
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D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode When performing ...
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Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows ...
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area in P2 area On-chip I/O access No Data TLB miss exception PR R/W? R Data TLB protection violation exception Cache access in copy-back mode Figure 3.10 Flowchart of ...
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Instruction access to virtual address (VA area in P2 area 0 Access prohibited CCR.ICE? No VPNs match and Yes Hardware ITLB Search UTLB miss handling Yes Record in ITLB Match? No ...
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MMU Functions 3.5.1 MMU Hardware Management The SH7750 Series supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR ...
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MMUCR LRUI Entry specification PTEH VPN Entry 0 ASID [7:0] VPN [31:10] Entry 1 ASID [7:0] VPN [31:10] Entry 2 ASID [7:0] VPN [31:10] Entry 63 ASID [7:0] VPN [31:10] ...
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Avoiding Synonym Problems When 1- or 4-kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address ...
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MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page ...
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Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. ...
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Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not ...
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Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated ...
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Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary ...
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Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued ...
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Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external ...
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ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field ...
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ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data ...
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ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data ...
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In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed ...
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UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data ...
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UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data ...
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Rev. 6.0, 07/02, page 94 of 986 ...
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Overview 4.1.1 Features An SH7750 or SH7750S has an on-chip 8-kbyte instruction cache (IC) for instructions and 16- kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 kbytes) may alternatively be used as ...
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Table 4.3 Features of Store Queues Item Store Queues Capacity 2 32 bytes Addresses H'E000 0000 to H'E3FF FFFF Write Store instruction (1-cycle write) Write-back Prefetch instruction (PREF instruction) Access right MMU off: according to MMUCR.SQMD MMU on: according to ...
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Register Descriptions There are three cache and store queue related control registers, as shown in figure 4.1. CCR 31 30 EMODE * QACR0 31 QACR1 31 *: SH7750R only indicates reserved bits: 0 must be specified in a write; ...
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EMODE: Double-sized cache mode bit In the SH7750R, this bit indicates whether the double-sized cache mode is used or not. This bit is reserved in the SH7750 and SH7750S. The EMODE bit must not be written to while the cache ...
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WT: Write-through bit Indicates the P0, U0, and P3 area cache write mode. When address translation is performed, the value of the WT bit in the page management information has priority. 0: Copy-back mode 1: Write-through mode OCE: OC enable ...
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Effective address OIX [13 MMU 19 511 Compare Hit signal Figure 4.2 Configuration of Operand Cache(SH7750, SH7750S) Rev. 6.0, 07/02, page 100 of 986 RAM area determination ORA [12] ...
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Effective address RAM area judgment OIX ORA [13] Entry selection 22 Address array 9 (way 0, way 1) Tag address 0 MMU 19 511 19 bits Compare Compare way 0 way 1 Hit signal Figure 4.3 Configuration ...
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Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset. V bit (validity bit) Indicates that valid data is stored ...
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Read Operation When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read ...
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Write Operation When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read ...
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Cache miss (with copy-back/write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is ...
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RAM Mode Setting CCR.ORA to 1 enables half of the operand cache to be used as RAM. In the SH7750 or SH7750S, the 8 kbytes of operand cache entries 128 to 255 and 384 to 511 are used as ...
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Examples of RAM usage with the SH7750R is shown below. In SH7750/SH7750S-compatible mode (CCR.EMODE = 0) H'7C00 0000 to H'7C00 1FFF (8 kB): RAM area (entries 256 to 511) H'7C00 2000 to H'7C00 3FFF (8 kB): RAM area (entries 256 ...
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Prefetch Operation The SH7750 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss known that a cache miss will result from a read or write operation, ...
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Effective address IIX [12 Address array Tag 0 MMU 19 255 19 bits Compare Hit signal Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S [11:5] Longword (LW) selection 3 Data ...
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Effective address 31 25 IIX [12] Entry selection 22 Address array 8 (way 0, way1) Tag address 0 MMU 19 255 19 bits Compare Compare way 0 Hit signal Figure 4.7 Configuration of Instruction Cache (SH7750R) Tag Stores the upper ...
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LRU (SH7750R only 2-way set-associative cache items of data can be registered in the cache at each entry address (address: 12–5). When an entry is registered, the LRU bit indicates which of the 2 ways ...
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Memory-Mapped Cache Configuration (SH7750, SH7750S) To enable the IC and managed by software, their contents can be read and written area program with a MOV instruction in privileged mode. Operation is not guaranteed ...
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This operation is used to invalidate a specific IC entry ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and ...
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Address field Data field L : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.9 Memory-Mapped IC Data Array 4.5.3 OC Address Array The OC ...
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OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in ...
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The following two kinds of operation can be used on the OC data array data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field ...
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IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field ...
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Address field Data field V : Validity bit A : Association bit : Reserved bits (0 write value, undefined read value) Figure 4.12 Memory-Mapped IC Address Array 4.6.2 IC Data ...
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Address field Data field L : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.13 Memory-Mapped IC Data Array 4.6.3 OC Address Array The OC ...
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When a write is performed to a cache line for which the U bit and V bit are both 1, after write- back of that cache line, the tag, U bit, and V bit specified in the data field are ...
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The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array data array read Longword data is read into the data field from the data ...
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Store Queues The SH7750 Series supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. In the SH7750S or SH7750R, if the SQs are not used the low power dissipation power-down modes, in which SQ functions ...
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SQ can be written to without a penalty cycle, but writing to the SQ involved in the transfer to external memory is deferred until the transfer is completed. The SQ transfer destination external memory address bit [28:0] ...
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SQ Protection Determination of an exception in a write transfer to external memory (PREF instruction) is performed as follows according to whether the MMU off. In the SH7750 or SH7750S ...
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SQ Usage Notes If an exception occurs within the three instructions preceding an instruction that writes the SH7750 and SH7750S, a branch may be made to the exception handling routine after execution of the SQ ...
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Example 3: When an instruction that generates an exception does not branch using a branch instruction Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an ...
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Overview 5.1.1 Features Exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the CPU in case of abnormal events. For example, if the executing instruction ends abnormally, appropriate action must ...
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Register Descriptions There are three registers related to exception handling. Addresses are allocated to these registers, and they can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 ...
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Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15(SGR), and ...
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Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Category Mode Exception Reset Abort type Power-on reset Manual reset H-UDI reset Instruction TLB ...
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Table 5.2 Exceptions (cont) Exception Execution Category Mode Exception Interrupt Completion Nonmaskable interrupt type External interrupts Peripheral module interrupt (module/ source) Priority Priority Level Order 3 — IRL3–IRL0 ...
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Table 5.2 Exceptions (cont) Exception Execution Category Mode Exception Interrupt Completion Peripheral type module interrupt (module/ source) Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). Exception ...
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SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers may be set automatically by hardware, depending on the exception. For details, see section 5.6, Description of Exceptions. Also, see section 5.6.4, Priority Order with ...
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Pipeline flow: IF Instruction n Instruction n+1 IF Instruction n+2 Instruction n+3 Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling: TLB miss (instruction ...
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Exception Requests and BL Bit When the BL bit exceptions and interrupts are accepted. When the BL bit and an exception other than a user break is generated, the CPU's internal ...
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Resets (1) Power-On Reset Sources: SCK2 pin high level and 5(6(7 pin low level When the watchdog timer overflows while the WT/,7 bit is set to 1 and the RSTS bit is cleared WTCSR. For details, ...
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Manual Reset Sources: SCK2 pin low level and 5(6(7 pin low level When a general exception other than a user break occurs while the BL bit is set When the watchdog timer overflows while the ...
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H-UDI Reset Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) Transition address: H'A000 0000 Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made H'A000 ...
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Instruction TLB Multiple-Hit Exception Source: Multiple ITLB address matches Transition address: H'A000 0000 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set ...
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Operand TLB Multiple-Hit Exception Source: Multiple UTLB address matches Transition address: H'A000 0000 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set ...
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General Exceptions (1) Data TLB Miss Exception Source: Address mismatch in UTLB address comparison Transition address: VBR + H'0000 0400 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding ...
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Instruction TLB Miss Exception Source: Address mismatch in ITLB address comparison Transition address: VBR + H'0000 0400 Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number ...
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Initial Page Write Exception Source: TLB is hit in a store access, but dirty bit Transition address: VBR + H'0000 0100 Transition operations: The virtual address (32 bits) at which this exception occurred is set in ...
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Data TLB Protection Violation Exception Source: The access does not accord with the UTLB protection information (PR bits) shown below. PR Privileged Mode 00 Only read access possible 01 Read/write access possible 10 Only read access possible 11 Read/write ...
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Instruction TLB Protection Violation Exception Source: The access does not accord with the ITLB protection information (PR bits) shown below. PR Privileged Mode 0 Access possible 1 Access possible Transition address: VBR + H'0000 0100 Transition operations: The virtual ...
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Data Address Error Sources: Word data access from other than a word boundary (2n +1) Longword data access from other than a longword data boundary (4n + +3) Quadword data access from other than ...
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Instruction Address Error Sources: Instruction fetch from other than a word boundary (2n +1) Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode Transition address: VBR + H'0000 0100 Transition operations: The virtual address (32 bits) at which ...
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Unconditional Trap Source: Execution of TRAPA instruction Transition address: VBR + H'0000 0100 Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The values of SR ...