IDT723624 Integrated Device Technology, Inc., IDT723624 Datasheet

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... Logic FIFO1 Programmable Flag Timing Offset Registers Mode FIFO2 Status Flag Logic Read Write Pointer Pointer RAM ARRAY 256 512 x 36 1,024 x 36 Mail 2 Register 1 IDT723624 IDT723634 IDT723644 MBF1 36 EFB/ORB AEB FWFT FFB/IRB AFB 36 FIFO2, MRS2 Mail2 Reset PRS2 Logic CLKB ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 The IDT723624/723634/723644 is a monolithic, high-speed, low- power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies MHz and has read access times as fast as 8 ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions ...

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... Initiating any operation (by activating CC control inputs) will immediately take the device out of the power down state. The IDT723624/723634/723644 are characterized for operation from 0°C to 70°C. Industrial temperature range (- + available. They are fabricated using IDT’s high speed, submicron CMOS technology. ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 Symbol Name I/O A0-A35 Port A Data I/O 36-bit bidirectional data port for side A. AEA Port A Almost- O Programmable Almost-Empty flag synchronized to CLKA LOW when the number of words in FIFO2 is less Empty Flag than or equal to the value in the Almost-Empty A Offset register, X2. ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 Symbol Name I/O FS1/SEN Flag Offset I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset register ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 Symbol V Supply Voltage Range CC (2) V Input Voltage Range I V (2) Output Voltage Range O I Input Clamp Current ( Output Clamp Current ( Continuous Output Current (V OUT I Continuous Current Through Storage Temperature Range STG NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under " ...

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... S outputs were disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of IDT723624/723634/723644 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With I ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 (Commercial ± Symbol Parameter f Clock Frequency, CLKA or CLKB S t Clock Cycle Time, CLKA or CLKB CLK t Pulse Duration, CLKA or CLKB HIGH CLKH t Pulse Duration, CLKA and CLKB LOW CLKL t Setup Time, A0-A35 before CLKA and B0-B35 before CLKB DS Setup Time, CSA and W/RA before CLKA ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 (Commercial ± Symbol Parameter t Access Time, CLKA to A0-A35 and CLKB to B0-B35 A Propagation Delay Time, CLKA to FFA/IRA and CLKB to FFB/IRB t WFF Propagation Delay Time, CLKA to EFA/ORA and CLKB to EFB/ORB t REF Propagation Delay Time, CLKA to AEA and CLKB to AEB ...

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... After power up, a Master Reset operation must be performed by providing a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, each of the two FIFO memories of the IDT723624/723634/723644 undergoes a complete reset by taking its associated Master Reset (MRS1, MRS2) input LOW for at least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions ...

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... IDT723634, or IDT723644, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 252 for the IDT723624 508 for the IDT723634; and 1 to 1,020 for the IDT723644. After all the offset registers are programmed from Port A, the Port B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal operation ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are active outputs when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB) These are dual purpose flags. In the FWFT mode, the Output Ready (ORA, ORB) function is selected ...

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... IDT723624, IDT723634, or IDT723644 respectively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [256- (Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723624, IDT723634, or IDT723644 respectively. Note that a data word present in the FIFO output register has been read from memory. ...

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... Master Reset, by the time the Full/Input Ready flag is set HIGH, as shown in Figure 2. Only 36-bit long word data is written to or read from the two FIFO memories on the IDT723624/723634/723644. Bus-matching operations are done after COMMERCIAL TEMPERATURE RANGE data is read from the FIFO1 RAM and before data is written to the FIFO2 RAM. ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 BYTE ORDER ON PORT SIZE BYTE ORDER ON PORT SIZE SIZE SIZE SIZE A35 A27 A26 A18 A17 B35 B27 B26 B18 B17 (a) LONG WORD SIZE B35 B27 B26 B18 B17 B9 A B35 B27 ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA CLKB t RSTS MRS1 BE/FWFT SPM FS1,FS0 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF MBF1 NOTES: 1. FIFO2 (MRS2) Master Reset is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset (MRS1) must toggle simultaneously with MRS2. ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA 1 4 MRS1, MRS2 t FSS t FSH SPM t FSS t FSH 0,0 FS1,FS0 FFA/IRA ENA A0-A35 CLKB FFB/IRB NOTES: is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA 1 ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ENA A35 NOTE: 1. Written to FIFO1. Figure 7. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes) t CLK ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB FFB/IRB HIGH CSB W/RB MBB ENB B0-B17 (1) SIZE MODE BM SIZE NOTE selected at Master Reset; BM and SIZE must be static throughout device operation. Figure 9. Port B Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes) ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t CLKH CLKB EFB/ORB HIGH CSB W/RB MBB ENB t EN B0-B35 (Standard Mode B0-B35 (FWFT Mode) NOTE: 1. Read From FIFO1. (1) SIZE MODE BM SIZE BE A35-A27 NOTE selected at Master Reset; BM and SIZE must be static throughout device operation. ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB EFB/ORB HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode) t MDV B0-B8 (FWFT Mode) NOTE: 1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate. (1) SIZE MODE BM SIZE NOTE selected at Master Reset; BM and SIZE must be static throughout device operation. ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA CSA LOW WRA HIGH t ENS2 MBA t ENS2 ENA IRA HIGH t DS A0-A35 W1 t SKEW1 CLKB ORB FIFO1 Empty CSB LOW W/RB HIGH LOW MBB ENB Old Data in FIFO1 Output Register B0-B35 NOTES: 1 ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA CSA LOW WRA HIGH t t ENS2 MBA t t ENS2 ENA FFA HIGH A0-A35 W1 t SKEW1 CLKB EFB FIFO1 Empty CSB LOW W/RB HIGH LOW MBB ENB B0-B35 NOTES: is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge 1 ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH B0-B35 t SKEW1 CLKA ORA FIFO2 Empty CSA LOW LOW W/RA LOW MBA ENA Old Data in FIFO2 Output Register ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENS2 ENH ENB FFB HIGH B0-B35 t SKEW1 CLKA EFA FIFO2 Empty CSA LOW LOW W/RA LOW MBA ENA A0-A35 NOTES: is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge 1 ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB ORB HIGH B0-B35 Previous Word in FIFO1 Output Register CLKA IRA FIFO1 Full CSA LOW W/RA HIGH MBA ENA A0-A35 NOTES: 1 ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB EFB HIGH B0-B35 Previous Word in FIFO1 Output Register CLKA FFA FIFO1 Full CSA LOW W/RA HIGH MBA ENA A0-A35 NOTES: is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA ORA HIGH A0-A35 Previous Word in FIFO2 Output Register CLKB IRB FIFO2 FULL CSB LOW W/RB LOW MBB ENB B0-B35 NOTES: 1 ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH A0-A35 Previous Word in FIFO2 Output Register CLKB FFB FIFO2 Full CSB LOW W/RB LOW MBB ENB B0-B35 NOTES: is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle ...

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... FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO Maximum FIFO Depth = 256 for the IDT723624, 512 for the IDT723634, 1,024 for the IDT723644. ...

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... FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO Maximum FIFO Depth = 256 for the IDT723624, 512 for the IDT723634, 1,024 for the IDT723644. ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB t ENS1 CSB t ENS1 W/RB t ENS2 MBB t ENS2 ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA t EN A0-A35 FIFO2 Output Register NOTE Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don’t care inputs). In this first case A0-A17 will have valid data (A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don’ ...

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... IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PZL t PLZ Low-Level Output t PZH High-Level Output t PHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTE: 1 ...

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IDT X XX XXXXXX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. 10/04/2000 pgs. 1 through 35, except pgs. 20, 24-26, 32 and 33. 03/22/2001 pgs. 6 and 7. 08/01/2001 pgs ...