AM188EM Advanced Micro Devices, AM188EM Datasheet
AM188EM
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AM188EM Summary of contents
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... High-level Data Link Control (HDLC) and the Universal Serial Bus (USB). © Copyright 2000 Advanced Micro Devices, Inc. All rights reserved – General-purpose DMA (4 channels) – Programmable I/O (48 PIO signals) – Interrupt Controller (36 maskable interrupts) n Memory and Peripheral Interface – ...
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ORDERING INFORMATION Am186CC –50 K Valid Combinations Am186CC–25 Am186CC–40 KC\W Am186CC–50 Am186CC–25 KI\W Am186CC–40 2 Am186™CC Communications Controller Data Sheet C \W LEAD FORMING \W=Trimmed and Formed TEMPERATURE RANGE C= Am186CC Commercial ( Am186CC Industrial (T where: T ...
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TABLE OF CONTENTS Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 1 Ordering Information .................................................................................................................... 2 Logic Diagram by Interface .......................................................................................................... 6 Logic Diagram by Default Pin Function ....................................................................................... 7 Pin Connection Diagram—160-Pin PQFP Package .................................................................... 8 Pin and Signal Tables ...
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Maximum Load Derating ............................................................................................................ 47 Power Supply Current ................................................................................................................ 47 Thermal Characteristics ............................................................................................................. 48 PQFP Package ..................................................................................................................... 48 Commercial and Industrial Switching Characteristics and Waveforms ...................................... 49 Switching Characteristics over Commercial and Industrial Operating Ranges ......................................58 Appendix A—Pin Tables ............................................................................................................A-1 ...
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Figure 31. PCM Highway Waveforms (Timing Slave) ............................................................ 75 Figure 32. PCM Highway Waveforms (Timing Master) .......................................................... 76 Figure 33. DCE Transmit Waveforms .................................................................................... 77 Figure 34. DCE Receive Waveforms ..................................................................................... 77 Figure 35. USB Data Signal Rise and Fall ...
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LOGIC DIAGRAM BY INTERFACE CLKOUT Reset/ RES Clocks RESOUT X1 X2 Address and A19–A0 20 Address/Data AD15–AD0 16 Buses ALE ARDY BHE BSIZE8 DEN DS 2 DRQ1–DRQ0 / DT/R Bus Status and HLDA Control HOLD RD 3 S2– ...
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LOGIC DIAGRAM BY DEFAULT PIN FUNCTION CLKOUT Reset/ RES Clocks RESOUT X1 X2 Address and A19–A0 20 Address/Data Buses AD15–AD0 16 ALE [PIO33] ARDY [PIO8] BHE [PIO34] {ADEN} BSIZE8 DEN [DS] [PIO30] DRQ1 DT/R [PIO29] HLDA {CLKSEL1} Bus Status and ...
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PIN CONNECTION DIAGRAM—160-PIN PQFP PACKAGE SDEN 3 SCLK 4 SDATA 5 PCS0 {USBSEL1} 6 PCS1 {USBSEL2} 7 PCS2 8 PCS3 9 PCS4 {CLKSEL2} 10 PCS5 11 PCS6 PCS7 14 ARDY 15 SRDY ...
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PIN AND SIGNAL TABLES Table 1 on page 10 and Table 2 on page 11 show the ...
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Table 1. PQFP Pin Assignments—Sorted by Pin Number Pin No. Name—Left Side Pin No. Name—Bottom Side Pin No SDEN 42 3 SCLK 43 4 SDATA 44 5 PCS0 {USBSEL1 PCS1 {USBSEL2 ...
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Table 1. PQFP Pin Assignments—Sorted by Pin Number Pin No. Name—Left Side Pin No. Name—Bottom Side Pin No. 38 AD2 78 39 AD10 Notes: 1. See Table 29, “PIOs Sorted by PIO Number,” on page ...
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Table 2. PQFP Pin Assignments—Sorted by Signal Name Signal Name Pin No. Signal Name AD11 47 INT4 AD12 52 INT5 AD13 67 INT6 AD14 87 INT7 AD15 93 INT8/PWD ALE 19 LCS/RAS0 ARDY 14 MCS0 {UCSX8} BHE {ADEN} 20 MCS1/CAS1 ...
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Signal Descriptions Table 4 on page 14 contains a description of the Am186CC controller signals. Table 3 describes the terms used in Table 4. The signals are organized alphabetically within the following functional groups: n Bus interface/general-purpose DMA request (page ...
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Multiplexed Signal Name Signal(s) BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST A19–A0 — AD15–AD0 — ALE [PIO33] ARDY [PIO8] 14 Am186™CC Communications Controller Data Sheet Table 4. Signal Descriptions Type Description O Address Bus supplies nonmultiplexed memory or I/O addresses to the system ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) BHE [PIO34] {ADEN} BSIZE8 — DEN [DS] [PIO30] [DS] DEN PIO30 DT/R [PIO29] DRQ1 — [DRQ0] PIO9 Am186™CC Communications Controller Data Sheet O Bus High Enable: During a memory ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Signal(s) HLDA {CLKSEL1} HOLD — RD — S6 — SRDY [PIO35] 16 Am186™CC Communications Controller Data Sheet Type Description O Bus-Hold Acknowledge is asserted to indicate to an external bus master that ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) S2 — S1 — S0 {USBXCVR} WHB — WLB — WR [PIO15] CLOCKS/RESET/WATCHDOG TIMER CLKOUT — Am186™CC Communications Controller Data Sheet O Bus Cycle Status 2–0 indicate to the ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Signal(s) RES — RESOUT — [UCLK] [USBSOF] [USBSCI] PIO21 USBX1 — USBX2 — X1 — X2 — PINSTRAPS (See Table 31, “Reset Configuration Pins (Pinstraps),” on page A-10.) RESERVED RSVD_101 UTXDPLS RSVD_102 ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) POWER AND GROUND V (15) — (1) — _USB (1) — (15) — (1) — _USB (1) ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Signal(s) [PCS7] PIO31 [PCS6] PIO32 [PCS5] PIO2 [PCS4] PIO3 {CLKSEL2} PCS3 — PCS2 — PCS1 [PIO14] {USBSEL2} PCS0 [PIO13] {USBSEL1} UCS {ONCE} DRAM [CAS1] MCS1 [CAS0] MCS2 [RAS1] [MCS3] PIO5 [RAS0] LCS ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) INTERRUPTS NMI — [INT8] [PWD] PIO6 [INT7] PIO7 [INT6] PIO19 INT5–INT0 — Also configurable as interrupts are PIO5, PIO15, PIO27, PIO29, PIO30, PIO33, PIO34, and PIO35. (See the Am186™CC/CH/CU ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Signal(s) PROGRAMMABLE I/O (PIOS) PIO47–PIO0 (For multiplexed signals see Table 29, “PIOs Sorted by PIO Number,” on page A-8 and Table 30, “PIOs Sorted by Signal Name,” on page A-9.) PROGRAMMABLE TIMERS ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) [CTS_U] [DCE_TCLK_D] [PCM_FSC_D] PIO24 [RTR_U] DCE_RCLK_D [PCM_CLK_D] PIO25 High-Speed UART [RXD_HU] PIO16 TXD_HU — [CTS_HU] [DCE_CTS_D] [PCM_TSC_D] PIO46 [RTR_HU] [DCE_RTR_D] PIO47 SYNCHRONOUS SERIAL INTERFACE (SSI) [SCLK] PIO11 [SDATA] PIO12 ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Signal(s) DCE_TCLK_A [GCI_FSC_A] [PCM_FSC_A] [DCE_CTS_A] [PCM_TSC_A] PIO17 [DCE_RTR_A] PIO18 HDLC Channel B (DCE) [DCE_RXD_B] [PCM_RXD_B] PIO36 [DCE_TXD_B] [PCM_TXD_B] PIO37 [DCE_RCLK_B] [PCM_CLK_B] PIO40 [DCE_TCLK_B] [PCM_FSC_B] PIO41 [DCE_CTS_B] [PCM_TSC_B] PIO38 [DCE_RTR_B] PIO39 HDLC Channel ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) [DCE_TXD_D] [TXD_U] (UART) [PCM_TXD_D] PIO20 DCE_RCLK_D [RTR_U] (UART) [PCM_CLK_D] PIO25 [DCE_TCLK_D] [CTS_U] (UART) [PCM_FSC_D] PIO24 [DCE_CTS_D] [CTS_HU] (High- Speed UART) [PCM_TSC_D] PIO46 [DCE_RTR_D] [RTR_HU] (High- Speed UART) PIO47 HDLC ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Signal(s) [PCM_FSC_C] [DCE_TCLK_C] PIO23 [PCM_TSC_C] [DCE_CTS_C] PIO44 HDLC Channel D (PCM) [PCM_RXD_D] [RXD_U] (UART) DCE_RXD_D PIO26 [PCM_TXD_D] [TXD_U] (UART) [DCE_TXD_D] PIO20 [PCM_CLK_D] [RTR_U] (UART) DCE_RCLK_D PIO25 [PCM_FSC_D] [CTS_U] (UART) [DCE_TCLK_D] PIO24 [PCM_TSC_D] ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) [USBSCI] [UCLK] [USBSOF] PIO21 [USBSOF] [UCLK] [USBSCI] PIO21 UTXDMNS RSVD_102 UTXDPLS RSVD_101 UXVOE RSVD_103 UXVRCV RSVD_104 Am186™CC Communications Controller Data Sheet STI USB Sample Clock Input is used to ...
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ARCHITECTURAL OVERVIEW The architectural goal of the Am186CC microcontroller is to provide comprehensive communications features on a processor r unning the widely known x86 instr uction set. The Am186CC microcontroller combines four HDLC channels, a USB peripheral controller, and general ...
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Four independent Time Slot Assigners (TSAs) provide flexible time slot allocation – Allows isolation of Time Division Multiplexed (TDM) time slot of choice from a variety of TDM carriers – 4096 sequential bits isolated – TDM bus ...
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Shift Left 4 Bits Memory Figure 2. Two-Component Address Example Table 5. Segment Register Selection Rules Memory Reference Needed Segment Register Used Implicit Segment Selection Rule Instructions ...
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Four HDLC Channels and Four TSAs The Am186CC microcontroller provides four HDLC channels that support the HDLC, SDLC, LAP-B, LAP-D, PPP, and v.120 protocols. The HDLC channels can also be used in transparent mode to support v.110. Each HDLC channel ...
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DMA to and/or from the serial ports using the general-purpose DMA channels. ...
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Timer 2 is not connected to any external pins. It can be used by software to generate interrupts can be polled for real-time coding and time-delay applications. Timer 2 can also be used as a prescaler to Timer ...
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Figure 4 on page 36 shows a bus cycle when address bus disable is in effect, which causes the AD bus to operate in a nonmultiplexed data-only mode. The A bus has the address during a read or write operation. ...
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The chip select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit. General enhancements over the original 80C186 include bus mastering (three-state) support ...
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CLKOUT A19–A0 AD7–AD0 (Read) AD15–AD8 (Read) AD15–AD0 (Write) LCS or UCS Figure 4. Am186CC Controller—Address Bus Disable In Effect 36 Am186™CC Communications Controller Data Sheet Address Data Phase Phase Address Data Data Data t ...
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In-Circuit Emulator Support Because pins are an expensive resource, many play a dual role, and the programmer selects PIO operation or an alternate function. However, a pin configured PIO may also be required for emulation support. Therefore, ...
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I Figure 5. ISDN Terminal Adapter System Application Figure 6. ISDN to Ethernet Low-End Router System Application 38 Am186™CC Communications Controller Data Sheet ...
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Figure 7. 32-Channel Linecard System Application Am186™CC Communications Controller Data Sheet 39 ...
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CLOCK GENERATION AND CONTROL The Am186CC controller clocks include the general system clock (CLKOUT), USB clock, transmitter/ receiver clocks for each HDLC channel, and the baud rate generator clock for UART and High-Speed UART. The SSI and the timers (Timers ...
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Clock Sharing by System and USB The system and USB clocks can be generated from a single source in one of two ways: n The system can run at 48 MHz by using the system clock for the USB clock. ...
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System Operating Frequency 0 MHz 20 MHz 16 MHz 4x Mode 2x Mode 1x Mode PLL Bypass 0-MHz to 24-MHz Xtal or Clock Mode PLL Bypass Mode 1 The crystal oscillator is not guaranteed above 40 MHz. Figure 9. Suggested ...
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External Clock Source The internal oscillator also can be driven by an external clock source. The external clock source should be connected to the input of the inverting amplifier ( ...
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POWER SUPPLY OPERATION CMOS dynamic power consumption is proportional to the square of the operating voltage multiplied by capacitance and operating frequency. Static system operation can reduce power consumption by enabling the system designer to reduce operating frequency when possible. ...
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ABSOLUTE MAXIMUM RATINGS Parameter Temperature under bias: Commercial Industrial Storage temperature 4 Voltage on 5-V-tolerant pins with respect to ground Voltage on other pins with respect to ground Sustained PIO current on any supply (V Sustained PIO current on any ...
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DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES Symbol Parameter V Output High voltage ( Output High voltage ( Output Low voltage ( 5-V tolerant Input High voltage IH5 V Input ...
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MAXIMUM LOAD DERATING All maximum delay numbers should be increased by 0.035 ns for every pF of load ( maximum of 150 pF) over the maximum load specified in Table 35, “Pin List Summary,” on page A-12. POWER ...
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THERMAL CHARACTERISTICS PQFP Package The Am186CC controller is specified for operation with case temperature ranges from 0•C to +100•C for 3.3 V ± 0.3 V (commercial). Case temperature is measured at the top center of the package as shown in ...
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COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS In the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. These periods are referred to as time states. A typical bus cycle is composed ...
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Table 9. Alphabetical Key to Switching Parameter Symbols Parameter No. Symbol t 49 ARYCH t 51 ARYCHL t 95 ARYHDSH t 89 ARYHDV t 52 ARYLCL t 96 ARYLDSH t 87 AVBL t 14 AVCH t 12 AVLL t 66 ...
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Table 9. Alphabetical Key to Switching Parameter Symbols (Continued) Parameter No. Description Symbol LCS active delay CLCSL t 16 MCS/PCS active delay CLCSV t 30 Data hold time CLDOX t 7 Data valid delay CLDV t 2 ...
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Table 9. Alphabetical Key to Switching Parameter Symbols (Continued) Parameter No. Symbol t 35 WHDEX t 34 WHDX t 33 WHLH t 32 WLWH USB Timing (Clocks UCHCK t 4 UCKHL t 1 UCKIN t 5 UCKLH t ...
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Table 9. Alphabetical Key to Switching Parameter Symbols (Continued) Parameter No. Description Symbol PCM (Master Delay time from CLK High to FSC High DCFH t 2 Delay time from CLK High to FSC Low DCFL GCI t 9 ...
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Table 10. Numerical Key to Switching Parameter Symbols Parameter No. Symbol 1 t DVCL 2 t CLDX 3 t CHSV 4 t CLSH 5 t CLAV 6 t CLAX 7 t CLDV 8 t CHDX 9 t CHLH 10 t ...
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Table 10. Numerical Key to Switching Parameter Symbols (Continued) Parameter No. Description Symbol 44 t CLKOUT High time CHCL 45 t CLKOUT rise time CH1CH2 46 t CLKOUT fall time CL2CL1 47 t SRDY transition setup time SRYCL 48 t ...
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Table 10. Numerical Key to Switching Parameter Symbols (Continued) Parameter No. Symbol DSHDIW 402 t COLV 403 t CHRAS 404 t CHCAS USB Timing (Clocks UCKIN 2 t UCLCK 3 t UCHCK 4 t UCKHL ...
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Table 10. Numerical Key to Switching Parameter Symbols (Continued) Parameter No. Description Symbol PCM (Master Delay time from CLK High to FSC High DCFH 2 t Delay time from CLK High to FSC Low DCFL GCI 1 t ...
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Switching Characteristics over Commercial and Industrial Operating Ranges In this section the following timings and timing waveforms are shown: n Read (page 58) n Write (page 61) n Software halt (page 64) n Peripheral (page 65) n Reset (page 66) ...
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Table 11. Read Cycle Timing Parameter No. Symbol Description 21 t DEN/DS inactive CEVDX 4 delay 22 t Control active CHCTV delay ALE High to LHAV address valid Read Cycle Timing Responses address float ...
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CLKOUT A19– AD15–AD0 ALE RD BHE LCS, UCS MCS3–MCS0, PCS7–PCS0 DEN, DS DT/R S2–S0 Notes not valid for the first fetch until the timing for parameter 3 (status active delay (t 60 Am186™CC Communications Controller ...
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Parameter No. Symbol Description General Timing Responses 3 t Status active delay CHSV 4 t Status and BHE CLSH inactive delay address and CLAV BHE valid delay 6 t Address hold CLAX 7 t Data valid delay ...
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Table 12. Write Cycle Timing Parameter No. Symbol Description Write Cycle Timing Responses 30 t Data hold time CLDOX 31 t Control inactive CVCTX 3,4 delay pulse width WLWH inactive to ALE WHLH 2 ...
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T4 CLKOUT A19– AD15—AD0 ALE WR WHB, WLB BHE LCS, UCS MCS3–MCS0, PCS7–PCS0 DEN DS DT/R S2–S0 Notes not valid for the first fetch until the timing for parameter 3 (status active delay (t Am186™CC ...
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Parameter No. Symbol Description 3 t Status active delay CHSV 4 t Status inactive CLSH delay address invalid CLAV delay 9 t ALE active delay CHLH 10 t ALE width LHLL 11 t ALE inactive delay CHLL ...
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Parameter No. Symbol Description 53 t Peripheral setup time INVCH 54 t Timer output delay CLTMV 55 t Queue status 0 output delay CHQ0SV 56 t Queue status 1 output delay CHQ1SV Notes: 1. All timing parameters are measured at ...
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Parameter No. Symbol Description 57 t RES setup time RESIN 61 t Reset delay CLRO Notes: 1. All timing parameters are measured at V are with the load values shown in Table 35, “Pin List Summary,” on page A-12. RES ...
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RES CLKOUT All Pinstrap 1, 2 Pins 1 AD15–AD0 All Other Outputs RESOUT Notes: 1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes. 2. For a list of all the pinstraps, refer ...
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Parameter No. Symbol Description Ready Timing Requirements 47 t SRDY transition setup time SRYCL 48 t SRDY transition hold time CLSRY 49 t ARDY resolution transition setup time ARYCH 50 t ARDY active hold time CLARX 51 t ARDY inactive ...
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CLKOUT 1 ARDY (Normally Not-Ready System) 2 ARDY (Normally Ready System) Notes normally not ready system, wait states are added after T3 until normally ready system, a wait state is added if t ...
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CLKOUT HOLD HLDA AD15–AD0, DEN MCS3–MCS0, PCS7–PCS0 A19–A0, S6, RD, WR, BHE, DT/R, S2–S0, WHB, WLB, UCS, LCS, ALE Figure 26. Entering Bus Hold Waveforms Case 1 Case 2 CLKOUT HOLD HLDA AD15–AD0, DEN MCS3–MCS0), PCS7–PCS0) A19–A0, S6, RD, WR, ...
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Parameter No. Symbol Description CLKIN Requirements for 4x PLL Mode period CKIN Low time (1.5 V) CLCK High time (1.5 V) CHCK fall time CKHL (3.5 to ...
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CLKOUT Figure 28. System Clock Timing Waveforms—Active Mode (PLL 1x Mode) No. Symbol Description CLKIN Requirements for 4x PLL Mode 1 t USBX1 period UCKIN 2 t USBX1 Low time (1.5 V) UCLCK 3 t USBX1 High ...
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No. Symbol Description 1 t Pulse width High Pulse width Low Frame setup Frame hold/clock Frame delay/clock Frame width High WFH 7 t Data delay/clock ...
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Table 21. PCM Highway Timing (Timing Slave) No. Symbol Description 1 t PCM clock period CLKP 2 t PCM clock High PCM clock Low Hold time from CLK Low to FSC valid HCF 5 ...
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PCM_CLK_x 14 1 PCM_FSC_x PCM_TXD_x PCM_RXD_x 11 12 PCM_TSC_x Notes: Note that the PCM_TXD_x outputs three-state. In the signal description and pin list summary tables, PCM_TXD_x is listed as O-LS-OD (totem pole output/programmable to hold ...
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Table 22. PCM Highway Timing (Timing Master) No. Symbol Description 1 t Delay time from CLK High to FSC High DCFH 2 t Delay time from CLK High to FSC Low DCFL Notes: 1. All timing parameters are measured at ...
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No. Symbol Description 1 t DCE clock period TCLKPER 2 t DCE clock High TCLKH 3 t DCE clock Low TCLKL 4 t DCE clock to output delay TCLKO 5 t DCE clock setup TCLKSU 6 t DCE clock hold ...
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Parameter No. Symbol Description 1 t Rise time ( pF Fall time ( pF Consecutive transition jitter (measured at crossover point) JR1 4 t Paired transition jitter (measured at crossover ...
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Parameter No. Symbol Description 1 t CLKOUT Low to SDEN valid CLEV 2 t CLKOUT Low to SCLK Low CLSL 3 t Data valid to SCLK High DVSH 4 t SCLK High to data invalid SHDX 5 t SCLK Low ...
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Parameter No. Symbol Description 1 t Data in setup DVCL 2 t Data in hold CLDX address valid delay CLAV 7 t Data valid delay CLDV address float delay CLAZ 20 t Control active ...
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CLKOUT AD15–AD0 A17, A15, A13, A11, A9, A7, A5, A3, A1 RAS0, RAS1 CAS0, RAS1 RD Figure 39. DRAM Read Cycle with Wait-States Waveform CLKOUT AD15–AD0 A17, A15, A13, A11, A9, A7, A5, A3, A1 RAS0, RAS1 CAS0, CAS1 WR ...
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CLKOUT AD15–AD0 A17, A15, A13, A11, A9, A7, A5, A3, A1 RAS0, RAS1 CAS0, CAS1 WR Figure 41. DRAM Write Cycle with Wait-States Waveform CLKOUT AD15–AD0 A17, A15, A13, A11, A9, A7, A5, A3, A1 RAS0, RAS1 CAS0, CAS1 RD ...
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APPENDIX A—PIN TABLES This appendix contains pin tables for the Am186CC controller. Several different tables are included with the following characteristics: Power-on reset pin defaults including pin numbers and multiplexed functions—Table 27 on page A-2. Multiplexed signal trade-offs—Table 28 page ...
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Table 27. Power-On Reset (POR) Pin Defaults Pin Multiplexed POR Default Number Signal Bus Interface Unit A0 30 — — — — — — — — ...
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Table 27. Power-On Reset (POR) Pin Defaults (Continued) Pin Multiplexed POR Default Number Signal S6 54 — SRDY 15 — WHB 95 — WLB 96 — — Chip Selects LCS 131 RAS0 MCS1 127 CAS1 MCS2 128 CAS0 ...
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Table 27. Power-On Reset (POR) Pin Defaults (Continued) Pin Multiplexed POR Default Number Signal PIO5 129 MCS3 PIO6 147 INT8 PIO7 146 INT7 PIO9 124 DRQ0 PIO10 2 SDEN PIO11 3 SCLK PIO12 4 SDATA PIO16 25 RXD_HU PIO17 123 ...
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Table 28. Multiplexed Signal Trade-offs DESIRED FUNCTION LOST FUNCTION Interface Name Pin Interface Memory 131 SRAM LCS DRAM MCS1 127 MCS2 128 MCS3 129 CAS0 128 DRAM SRAM CAS1 127 RAS0 131 RAS1 129 Synchronous Communications Interfaces DCE_RXD_A DCE 118 ...
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Table 28. Multiplexed Signal Trade-offs (Continued) DESIRED FUNCTION LOST FUNCTION Interface Name Pin Interface PCM PCM_RXD_C 153 DCE Channel Channel PCM_TXD_C 154 C C PCM_CLK_C 150 PCM_FSC_C 149 PCM_TSC_C 152 PCM PCM_RXD_D 158 DCE Channel Channel PCM_TXD_D 159 D D ...
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Table 28. Multiplexed Signal Trade-offs (Continued) DESIRED FUNCTION LOST FUNCTION Interface Name Pin Interface PIO13 5 PIO14 6 PIO15 16 PIO16 25 PIO17 123 PIO18 122 PIO19 145 PIO20 159 PIO21 22 PIO22 150 PIO23 149 PIO24 157 PIO25 156 ...
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PIO No. Pin No. Multiplexed Signal PIO0 144 TMRIN1 PIO1 143 TMROUT1 PIO2 10 PCS5 PIO3 9 PCS4 PIO4 126 MCS0 PIO5 129 MCS3 PIO6 147 INT8 PIO7 146 INT7 PIO8 14 ARDY PIO9 124 DRQ0 PIO10 2 SDEN PIO11 ...
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Signal PIO No. Pin No. ALE PIO33 ARDY PIO8 BHE PIO34 CTS_HU PIO46 CTS_U PIO24 DCE_CTS_A PIO17 DCE_CTS_B PIO38 DCE_CTS_C PIO44 DCE_RCLK_B PIO40 DCE_RCLK_C PIO22 DCE_RTR_A PIO18 DCE_RTR_B PIO39 DCE_RTR_C PIO45 DCE_RXD_B PIO36 DCE_RXD_C PIO42 DCE_TCLK_B PIO41 DCE_TCLK_C PIO23 DCE_TXD_B ...
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Table 31. Reset Configuration Pins (Pinstraps) Multiplexed Signal Name Signal(s) {ADEN} BHE PIO34 {CLKSEL1} HLDA {CLKSEL2} [PCS4] PIO3 {ONCE} UCS {UCSX8} [MCS0] PIO4 {USBSEL2} PCS1 PIO14 {USBSEL1} PCS0 PIO13 {USBXCVR} S0 Notes pinstrap is used to enable or ...
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Pin List Table Column Definitions The following paragraphs describes the individual columns of information in Table 35, “Pin List Summary,” on page A-12. The pins are grouped alphabetically by function. Note: All maximum delay numbers should be in- creased by ...
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Signal Name [Alternate Pin Function] No. {Pinstrap} Bus Interface Unit A10 50 A11 64 A12 65 A13 69 A14 70 ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Type Function] No. {Pinstrap} BHE [PIO34] 20 STI-PU [STI] [O] {ADEN} BSIZE8 94 DEN [DS] 18 [PIO30] STI-PU [STI] [O] [DRQ0] STI-PD 124 PIO9 STI-PD [STI] [O] DRQ1 105 STI-PD ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Function] No. {Pinstrap} PCS3 8 [PCS4] PIO3 9 STI-PU [STI] [O] {CLKSEL2} [PCS5] 10 PIO2 STI-PU [STI] [O] [PCS6] 11 PIO32 STI-PU [STI] [O] [PCS7] 13 PIO31 STI-PU [STI] [O] ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Type Function] No. {Pinstrap} [INT8] [PWD] 147 PIO6 STI-PU [STI] [O] NMI 115 Synchronous Communications Interfaces Channel A DCE_RXD_A [GCI_DD_A] 118 B-OD [PCM_RXD_A] DCE_TXD_A O-OD [GCI_DU_A] 119 B-OD [PCM_TXD_A] O-LS-OD ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Function] No. {Pinstrap} [DCE_RCLK_C] [PCM_CLK_C] 150 PIO22 STI-PD [STI] [O] [DCE_TCLK_C] [PCM_FSC_C] 149 PIO23 STI-PD [STI] [O] [DCE_CTS_C] [PCM_TSC_C] 152 PIO44 STI-PU [STI] [O] [DCE_RTR_C] 151 PIO45 STI-PU [STI] [O] ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Type Function] No. {Pinstrap} Synchronous Serial Interface [SCLK] 3 PIO11 STI-PU [STI] [O] [SDATA] 4 PIO12 STI-PU [STI] [O] [SDEN] 2 PIO10 STI-PD [STI] [O] Reserved Pins RSVD_104 104 [UXVRCV] ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Function] No. {Pinstrap} V 130 SS V 140 SS V 155 USB 82 SS A-18 Am186™CC Communications Controller Data Sheet Max POR ...
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APPENDIX B—PHYSICAL DIMENSIONS: PQR160, PLASTIC QUAD FLAT PACK (PQFP) Pin 160 25.35 REF Pin 1 I.D. Pin 40 3.20 3.60 0.25 Min Am186™CC Communications Controller Data Sheet 31.00 31.40 27.90 28.10 Pin 80 0.65 BASIC Pin 120 25.35 REF 27.90 ...
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B-2 Am186™CC Communications Controller Data Sheet ...
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... Description 80C186/80C188 16-bit microcontroller 80L186/80L188 Low-voltage, 16-bit microcontroller Am186™EM/Am188™EM High-performance, 16-bit embedded microcontroller Am186EMLV/Am188EMLV High-performance, 16-bit embedded microcontroller Am186ES/Am188ES High-performance, 16-bit embedded microcontroller Am186ESLV/Am188ESLV High-performance, 16-bit embedded microcontroller Am186ED High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or 16-bit external data bus ...
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Related Documents information ...
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World Wide Web Home Page To access the AMD home page go to: www.amd.com. Then follow the Embedded Processors link for information about E86 and Comm86 products. Questions, requests, and input concerning AMD’ ...
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C-4 Am186™CC Communications Controller Data Sheet ...
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INDEX A A19–A0 signals, 14 absolute maximum ratings, 45 AD15–AD0 signals, 14 address and data bus, 14, 17 address bus address bus disable in effect, 36 default operation, 35 description, 14, 17 ALE signal, 14 Am186CC controller architectural overview, 28 ...
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C-3 hotline and web, C-2 literature ordering, C-3 ordering the Am186CC controller, 2 third-party development support products, C-2 web home ...
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N NMI signal operating ranges, 45 ordering information package PQFP physical dimensions, B-1 PCM (pulse-code modulation) highway signal descriptions, 25 timing (timing master), 76 timing (timing slave), 74 waveforms (timing master), 76 waveforms (timing slave), 75 ...
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A-5 pin and signal tables, 9 pin assignments sorted by signal name, 11 signal descriptions, 14 signals related to reset, 67 SmartDMA channels, 31 software halt cycle timing, 64 software halt cycle waveforms, 64 SRDY ...
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X X1 signal signal, 18 Am186™CC Communications Controller Data Sheet Index-5 ...
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... Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimer The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci- fications and product descriptions at any time without notice ...