PEF81912H Infineon Technologies AG, PEF81912H Datasheet
PEF81912H
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PEF81912H Summary of contents
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Q-SMINT IX 2B1Q Second Gen. Modular ISDN NT (Intelligent eXtended) PEF 81912/81913 Version 1.3 Wir ed Communications ...
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... Edition March 2001 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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Q-SMINT IX 2B1Q Second Gen. Modular ISDN NT (Intelligent eXtended) PEF 81912/81913 Version 1.3 Wir ed Communications ...
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PEF 81912/81913 Revision History: Previous Version: Page Subjects (major changes since last revision) All Editorial changes, addition of notes for clarification etc. Table 1, Introduced new versions 81913 with extended performance of the U-interface Chapter 1.3 Chapter SCI: header description: ...
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PEF 81912/81913 Revision History: Previous Version: Page Subjects (major changes since last revision) Chapter AC-Timing SCI/parallel µC interface: enhanced timing specifications 5.6.2 Chapter 5.6.3 Chapter Added restriction for control interval t 5.6.3 Chapter Parameters of the UVD/POR Circuit: 5.6.5 defined ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.4.2.2 Access from the µC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ...
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Table of Contents 2.6.2 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.6.2 XFIFO - Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.9.5 HCI_CR - Control Register for HDLC and CI1 Data . . . . . . . . . . . . . . 204 4.9.6 MON_CR - Control Register Monitor Data . . . . . ...
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Table of Contents 5.6 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 41 M4, M5, M6 Bit Control in Receive Direction . . . . . . . . . . . . . . . . . . . . 77 Figure 42 M4, M5, M6 Bit ...
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List of Figures Figure 82 Q-SMINT IX Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . 156 Figure 83 Maximum Sinusoidal Ripple on Supply ...
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List of Tables Table 1 NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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List of Tables Table 41 Maximum Input Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview The PEF 81912 / 81913 (Q-SMINT IX) offers most features known from the PEB / PEF 8191 [12] and can hence replace the latter in its major applications. However, it does not replace the PEB/PEF 8191 in applications ...
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References [1] TS 102 080, Transmission and Multiplexing ; ISDN basic rate access; Digital transmission system on metallic local lines, ETSI, November 1998 [2] T1.601-1998 (Revision of ANSI T1.601-1992), ISDN-Basic Access Interface for Use on Metallic Loops for Application ...
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Second Gen. Modular ISDN NT (Intelligent eXtended) ® Q-SMINT IX Version 1.3 1.2 Features PEF 81912 Features known from the PEB/PEF 8191 • U-transceiver, S-transceiver and HDLC controller on one chip • Perfectly suited for low-cost intelligent NTs ...
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New Features • Reduced number of external components for external U-hybrid required • Optional use 2x20 • Pin Uref and the according external capacitor removed • Improved ESD (2 kV instead of <850 V) • Inputs ...
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Not Supported are ... • Integrated U-hybrid • ’Self test request’ and ’Self test passed’ of U-transceiver • TE-mode of the S-transceiver • DECT-link capability • SRA (capacitive receiver coupling is not suited for S-feeding). • ’NT-Star’ with star ...
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Pin Configuration • /VDDDET 49 50 VDDa_SR 51 52 VSSa_SR PS1 XOUT 59 XIN 60 ...
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Block Diagram • SR1 SR2 SX1 S-Transceiver SX2 to µP IF TP1 Factory Tests TP2 IOM-2 Interface FSC DCL BCL DU DD Figure 2 Block Diagram Data Sheet XIN XOUT RST RSTO VDDDET Clock Generation POR/UVD D-Channel Arbitration HDLC ...
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Pin Definitions and Functions • Table 3 Pin Definitions and Functions Pin Symbol 2 VDDa_UR 1 VSSa_UR 62 VDDa_UX 63 VSSa_UX 51 VDDa_SR 52 VSSa_SR 46 VDDa_SX 45 VSSa_SX 29 VDDD 30 VSSD 13 VDDD 14 VSSD 32 FSC ...
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Table 3 Pin Definitions and Functions (cont’d) Pin Symbol 8 SDS1 7 SDS2 SCLK 26 AD5 27 SDR 27 AD6 Data Sheet Type Function O Serial Data Strobe1: Programmable strobe signal for time slot and/ or D-channel ...
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Table 3 Pin Definitions and Functions (cont’d) Pin Symbol 28 SDX 28 AD7 21 AD0 22 AD1 23 AD2 24 AD3 25 AD4 ...
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Table 3 Pin Definitions and Functions (cont’d) Pin Symbol 10 WR R/W 9 ALE 5 RST 6 RSTO 15 INT 18 MCLK 19 20 EAW 43 SX1 44 SX2 47 SR1 Data Sheet Type Function I Write Indicates a write ...
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Table 3 Pin Definitions and Functions (cont’d) Pin Symbol 48 SR2 60 XIN 59 XOUT 64 AOUT 61 BOUT 3 AIN 4 BIN 49 VDDDET 16 MTI 55 PS1 41 PS2 17 ACT 42 TP1 Data Sheet Type Function I ...
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Table 3 Pin Definitions and Functions (cont’d) Pin Symbol 50 TP2 56, 57, res 58 1) This function of pin EAW is different to that defined in Ref. [14] I: Input O: Output (Push-Pull) OD: Output (Open Drain) 1.8.1 Specific ...
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Test Modes The test patterns on the S-interface (‘2 kHz Single Pulses‘, ‘96 kHz Continuous Pulses‘) and on the U-interface (‘Data Through‘, ‘Send Single Pulses‘) are invoked via C/I codes (TM1, TM2, DT, SSP). Setting SRES.RES_U to ‘1‘ forces the ...
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IOM-2 Slave e.g. SLICOFI-2 Figure 4 Control via µP Interface Alternatively, the Q-SMINT IX can be controlled via b) the IOM -2 Interface - Access of on-chip registers via the Monitor channel with Header/Address/Data format (Device is Monitor slave) ...
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S IOM -2 IOM-2 Master e.g. UTAH Figure 5 Control via IOM -2 Interface Data Sheet C/I1 C/I0 MON INT 16 PEF 81912/81913 Overview U Register iomslave.vsd 2001-03-30 ...
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Functional Description 2.1 Microcontroller Interfaces The Q-SMINT IX supports either a serial or a parallel microcontroller interface. For applications where no controller is connected to the Q-SMINT IX microcontroller interface, register programming is done via the IOM -2 MONITOR ...
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Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola and to the Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data is transferred ...
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Write Access CS SCLK SDR SDX Read Access CS SCLK SDR SDX Figure 6 Serial Control Interface Timing Data Sheet Command/Address Header ...
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Programming Sequences The basic structure of a read/write access to the Q-SMINT IX registers via the serial control interface is shown in • write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 7 Serial Command Structure ...
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Header 40 : Non-interleaved A-D-A-D Sequences H The non-interleaved A-D-A-D sequences give direct read/write access to the address range 00 -7F and can have any length. In this mode SDX and SDR can be connected H H together allowing data ...
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Header 41 : Non-interleaved A-D-D-D Sequence H This sequence (header 41 interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. Generally, it can be used for any register access to the ...
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The occurrence of an edge on ALE, either positive or negative, at any time during the operation immediately selects the interface type (3). A return to one of the other interface types is possible only if a hardware reset is ...
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Direct Address Mode AMOD = ´1´ 7Fh 7Eh 7Dh 7Ch 04h 03h 02h 01h 00h Figure 8 Direct/Indirect Register Address Mode 2.1.3 Microcontroller Clock Generation The microcontroller clock is derived from the unregulated 15.36 MHz clock ...
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Reset Generation Figure 9 shows the organization of the reset generation of the Q-SMINT IX. •. 125µs C/I0 Code Change (Exchange Awake 125µs Watchdog Software Reset Register (SRES) RES_CI Reset RES_HDLC Functional Block RES_S RES_U Internal Reset ...
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The internal reset sources set the MODE1 register to its reset value. Table 9 Reset Source Selection RSS2 RSS1 Bit 1 Bit POR/UVD can be enabled/disabled via pin VDDDET • ...
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External Reset Input At the RST input an external reset can be applied forcing the Q-SMINT IX in the reset state. This external reset signal is additionally fed to the RSTO output. After release of an external reset, the C ...
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IOM -2 Interface The Q-SMINT IX supports the IOM -2 interface in terminal mode (DCL=1.536 MHz) according to the IOM -2 Reference Guide [13]. 2.3.1 IOM -2 Functional Description The IOM -2 interface consists of four lines: FSC, DCL, ...
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The frame is composed of three channels • Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of e.g. the U-transceiver. • Channel ...
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Figure 11 Architecture of the IOM -2 Handler Data Sheet PEF 81912/81913 Functional Description CDA Data Monitor Data TIC Bus Data C/I0 Data C/I1 Data D Data D/B1/B2 Data C/I0 Data FSC DCL BCL/SCLK SDS1 SDS2 ...
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Controller Data Access (CDA) The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide microcontroller access to the 12 IOM -2 time slots and more: • looping four independent PCM channels from ...
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TSa 1 0 Enable output (EN_O0) CDAx0 1 0 TSa a,b = 0...11 Figure 12 Data Access via CDAx0 and CDAx1 register pairs Looping and Shifting Data Figure 13 gives examples for typical configurations ...
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Looping Data .TSS: .DPS .SWAP b) Shifting Data TSa CDA10 .TSS: TSa .DPS .SWAP c) Switching Data TSa CDA10 .TSS: TSa .DPS .SWAP Figure 13 Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting (Switching) ...
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Figure 14 shows the timing of looping TSa from via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD. Figure 15 shows the timing of shifting data ...
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Shifting TSa TSb within one frame (a,b: 0...11 and b a+2) FSC DU TSa (DD) CDAxy b) Shifting TSa TSb in the next frame (a,b: 0...11 and ( <a) FSC DU TSa (DD) CDAxy ...
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Monitoring Data Figure 16 gives an example for monitoring of two IOM -2 time slots each simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots ...
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Monitoring TIC Bus Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring) bit in the control registers CRx. The TSDPx0 ...
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Table 10 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) STI STOV ...
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INT CIC CIC TIN TIN WOV WOV S S MOS MOS HDLC HDLC MASK ISTA Figure 17 Interrupt Structure of the Synchronous Data Transfer Figure 18 shows some examples based on the timeslot structure. Figure ...
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STI interrupt generated : STOV interrupt generated for a not acknowledged STI interrupt a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 b) Interrupts for data ...
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Serial Data Strobe Signal For time slot oriented standard devices at the IOM -2 interface, the Q-SMINT IX provides two independent data strobe signals SDS1 and SDS2. The two strobe signals can be generated with every 8-kHz-frame and are ...
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Figure 19 shows three examples for the generation of a strobe signal. In example 1 the SDS is active during channel B2 on IOM -2, whereas in the second example during IC2 and MON1. The third example shows a strobe ...
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The MONITOR channel protocol is described In the following section and shall illustrate this. The relevant control and status bits for transmission and reception are listed in Table 11 and Table 11 Transmit Direction Control/ Register Status Bit Control MOCR ...
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P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 20 MONITOR Channel Protocol (IOM Before ...
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In addition, it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable (MIE) to ’1’ result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to ’0’. This causes a MONITOR Data ...
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Since a double last-look criterion is implemented the receiver is able to receive the MON slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two ...
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IOM -2 Frame No. MX (DU) MR (DD) Figure 21 Monitor Channel, Transmission Abort requested by the Receiver • IOM -2 Frame No. MR (DU) MX (DD) Figure 22 Monitor Channel, Transmission Abort requested by the Transmitter • IOM ...
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MONITOR Channel Programming as a Master Device The master mode is selected by default if one of the microcontroller interfaces is selected. The monitor data is written by the microcontroller in the MOX register and transmitted via IOM -2 ...
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DU 1st byte value DU 2nd byte value DU 3rd byte value DU 4th byte value DU (nth + 3) byte value All registers can be read back when setting the R/W bit to ’1’. The Q-SMINT IX responds ...
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MASK U ST CIC TIN WOV S MOS HDLC INT Figure 24 MONITOR Interrupt Structure 2.3.4 C/I Channel Handling The Command/Indication channel carries real-time status information between the Q- SMINT IX and another device connected to the IOM -2. ...
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The C/I1 channel is accessed via registers CIR1 and CIX1. The connection of CIR1 and CIX1 to DD and DU, respectively, can be selected by setting bit HCI_CR.DPS_CI1. A change in the received C/I1 code is indicated by an interrupt ...
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IOM -2 Reference Guide to set the priority (8 or 10) of all HDLC-controllers connected to IOM -2, which is particularly useful for use of the Q-SMINT IX together with the UTAH. 2.3.5.1 Application Example for D-Channel Access Control Figure ...
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In the case of an access request by the Q-SMINT IX, the Bus Accessed-bit BAC (bit 5 of last octet of CH2 on DU, see indicated by a logical ’1’. If the bus is free, the Q-SMINT IX transmits its ...
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The Stop/Go bit is available to other layer-2 devices connected to the IOM -2 interface to determine if they can access the D channel in upstream direction. • MON Figure 28 Structure of Last Octet of ...
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Table 13 Q-SMINT IX Configuration Settings in Intelligent NT Applications Functional Configuration Block Description Layer 1 Select Intelligent NT mode Layer 2 Enable S/G bit and TIC bus evaluation Note: For mode selection in the S_MODE register the MODE1/2 ...
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D=0) & [BAC = 1 or (BAC = 0 & CNT BAC = d.c. DCI = 0 S ACCESS 1) S Setting DCI = 1 causes ...
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Local D-Channel Controller Transmits Upstream In the initial state (’Ready’ state) neither the local D-channel sources nor any of the terminals connected to the S-bus transmit in the D-channel. The Q-SMINT IX S-transceiver thus receives BAC = “1” (IOM ...
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Activation/Deactivation of IOM The deactivation procedure of the IOM -2 interface is shown in Figure 30. After detecting the code DI (Deactivation Indication) the Q-SMINT IX responds by transmitting DC (Deactivation Confirmation) during subsequent frames and stops the timing ...
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A deactivated IOM -2 can be reactivated by one of the following methods: • Pulling pin DU line low: – directly at the IOM -2 interface – via the µP interface with "Software Power Up" (IOM_CR:SPU bit) • Pulling pin ...
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U-Transceiver The state machine of the U-Transceiver is based on the NT state machine in the PEB / PEF 8191 documentation [12]. Note: ’Self test request’ and ’Self test passed’ are not executed by the U-transceiver The U-transceiver is ...
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Table 15 U-Superframe Format Fram- ing Quat 1 – 9 Position s Bit 1 – 18 Position s Super Basic Sync Frame # Frame # Word 1 1 ISW ...
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DEA Deactivation bit – CSO Cold Start Only – UOA U-Only Activation – SAI S-Activity Indicator – FEBE Far-end Block Error – PS1 Power Status Primary Source – PS2 Power Status Secondary Source PS2 = (1) –> Secondary power ...
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U -Deframer 2B1Q (M-bit handling acc. to ETR080 2B1Q Decoding Figure 34 U Deframer - Data Flow Scheme 2B1Q 2.4.2 Maintenance Channel The last three symbols (6 bits) of each basic frame are used ...
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Access from the µC Interface The maintenance data to be transmitted can be programmed by writing the internal EOCW/M4W/M56W registers. 2.4.2.3 Availability of Maintenance Channel Information Transmission of the Maintenance channel data is only possible if a superframe is ...
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Note that the point of time when the 6 ms and 12 ms interrupts are generated within basic frame #1 and #5 is not fixed and may vary. • 6ms Interrupt #1 Frame No. max. 3 Base Frames 12ms Interrupt ...
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EOC Interrupt #1 Frame No. µC read access time max. 3 Base Frames set active in frame #1 if value has been updated M4 Interrupt #1 Frame ...
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The data/message indicator needs to be set to (1) to indicate that the information field contains a message. If set to (0), numerical data is transferred to the NT. Currently no numerical data transfer to or from the NT is ...
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Table 18 Usage of Supported EOC-Commands(cont’d) Hex- Function code i1- LB1 Closes B1 loop-back in NT. All B1-channel data will be looped back within the Q-SMINT IX U-transceiver. The bits LB1 and U/IOM are set in the ...
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MFILT.EOC EOCR Register Processor Figure 37 EOC Message Reception • EOCW Figure 38 EOC Command/Message Transmission Data Sheet U Receive Superframe EOC Message Filtering Last Verified EOC Message EOC Echo U-Rx Frame Processor µC EOC Command/ Message every 6 ...
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EOC Operating Modes The EOC operating modes are programmable in the MFILT register (see Chapter 4.11.2) EOC Auto Mode – Acknowledgement: All received EOC-frames are echoed back to the exchange immediately without triple-last-look address other than (000) ...
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Reporting: This mode is almost identical to the Transparent Mode 6 ms. But a report to the µ interrupt takes place only change in the EOC message has been detected. – Execution: No automatic execution ...
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EOC Automode Table 19 EOC Auto Mode remarks input from µC Access to EOCW register has direct impact on EOC TX. EOC EOC ...
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Transparent mode 6 ms) Table 20 Transparent mode 6 ms remarks input from µC EOC TX EOC RX report to µC Transparent mode ’@change’ Table 21 Transparent mode ’@change’ remarks input from µC EOC TX EOC RX report to µC ...
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Processing of the Overhead Bits M4, M5, M6 2.4.4.1 M4 Bit Reporting to the µC Four different validation modes can be selected and take effect on a per bit base. Only if the received M4 bit change has been ...
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M4 M5, M6 Figure 39 Maintenance Channel Filtering Options Figure 40 illustrates the point of time when a detected M4, M5, M6 bit change is reported to the µC and when it is reported to the state machine: • ...
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However, if the same filter is selected towards the state machine as programmed towards the µC, the user has to be aware that if CRC mode is active, the state machine is informed at the end of the next U-superframe. ...
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MFILT.M4 M4R Register UOA DEA ACT AIB EN/ DIS '1' MUX M4WMASK.Bit6 State Machine Figure 41 M4, M5, M6 Bit Control in Receive Direction • M4W Register NIB SAI M46 '1' M4WMASK MUX MUX '1'= M4W Reg. '0'= SM/ ...
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Cyclic Redundancy Check / FEBE bit An error monitoring function is implemented covering the and M4 data transmission of a U-superframe by a Cyclic Redundancy Check (CRC). The computed polynomial is: The check digits (CRC bits ...
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IOM -2 DD CRCOK=0 INT µC access DU µC access INT *0.0625 of a SFR is the 60 Quats offset of the NT transmit data. Figure 43 CRC-Process Data Sheet NT U (2B + D), M4 SFR(n) G(u) ...
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Block Error Counters The U-transceiver provides internal counters for far-end and near-end block errors. This allows a comfortable surveillance of the transmission quality at the U-interface. In addition, the occurrence of near-end errors, far-end errors, and the simultaneous occurrence ...
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The functional behavior of the Q-SMINT IX and the FEBE-counter depends on the mode selected: – EOC auto mode: The Q-SMINT IX will react with a permanently inverted upstream CRC. FEBE-detection stopped: no FEBE interrupt generated and FEBE-counter disabled – ...
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EOC µC Interface Transparent ISTAU.EOC=1 EOCR = 'NCC' ISTAU.FEBE/ ERROR COUNT NEBE=1 NEBE M56R.NEBE = '1' ISTAU.EOC=1 EOCR = 'RTN' ISTAU.EOC=1 EOCR = 'RCC' TEST.CCRC = '1' ERROR ISTAU.FEBE/ COUNT NEBE=1 FEBE M56R.FEBE = '1' ISTAU.EOC=1 EOCR = 'RTN' ...
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Table 23 presents all defined C/I codes. A new command or indication will be recognized as valid after it has been detected in two successive IOM criterion). Note: Unconditional C/I-Commands must be applied for at least 4 IOM -2 frames ...
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DC: Deactivation Confirmation DI: Deactivation Indication DR: Deactivation Request DT: Data Through test mode EI1: Error Indication 1 PU: Power-Up RES: Reset SSP: Send Single Pulses test mode TIM: Timing request 2.4.10 State Machines for Line Activation / Deactivation 2.4.10.1 ...
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Combinations of transition criteria are possible. Logical “AND” is indicated by “&” (TN & DC), logical “OR” is written “or” and for a negation “/” is used. The start of a timer is indicated with “TxS” (“x” being equivalent to ...
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Standard NT State Machine (IEC-Q / NTC-Q Compatible) • SN0 T14S Pending Timing DC Any State T14S DI SSP or SP C/I= 'SSP' Test DR SN0 Reset Any State DR Pin-RST or ARL C/I= 'RES' T12S SN1 EC-Training AL ...
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Note: The test modes ‘Data Through‘ (DT) and ‘Send Single Pulses‘ (SSP) are invoked via C/I codes ’DT’ and ’SSP’ according to forces the U-transceiver into test mode ‘Quiet Mode‘ (QM), i.e. the U-transceiver is hardware reset. If the Metallic ...
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TIM Timing The U-transceiver is requested to enter state ’IOM -2 Awaked’. U-Interface Events: ACT = 0/1 ACT-bit received from LT-side. – ACT = 1 requests the U-transceiver to transmit transparently in both directions. In the case of loop-backs, however, ...
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C/I-Indications AI Activation Indication The U-transceiver has established transparency of transmission. The downstream device is requested to establish layer-1 functionality. AIL Activation Indication Loopback The U-transceiver has established transparency of transmission. The downstream device is requested to establish a loopback ...
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Note: Alternating ± 3 symbols at 10 kHz. 2) Note: 4 Options for the test signal can be selected by register TEST kHz signal composed by alternating +/-3 or +/-1 transmit pulses. A series of single pulses ...
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Signals on IOM -2 The Data (B+B+D) is set to all ’1’s in all states besides the states listed in Dependence of Outputs 1) • Outputs denoted with Signal output on U depends on the received EOC command and on ...
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Description of the NT-States The following states are used: Alerting The wake-up signal TN is transmitted for a period of T11 either in response to a received wake-up signal start an activation procedure on the LT-side. ...
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Error S/T The downstream device error condition (EI1). The LT-side is informed by setting the ACT-bit to “0” (loss of transparency on the NT-side). IOM -2-Awaked The U-transceiver is deactivated, but may not enter the power-down mode. ...
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Synchronized 2 In this state the U-transceiver has received UOA = 1. This is a request to activate the downstream device. Test The test signal SP is issued as long as C/I=SSP is applied. For further details see Table 25. ...
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C/I changes at irrelevant state transitions are omitted, hence the number of interrupts is reduced. All advantages can be offered by the following minor changes to the existing state machine: • Table 28 Changes to achieve Simplified NT ...
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Table 28 Changes to achieve Simplified NT State Machine(cont’d) Change Not Supported State Transitions Data Sheet State Standard NT State Machine Test to IOM -2 none Awaked Reset to Alerting DI & NTAUTO all other no changes transitions 96 PEF ...
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SN0 T14S Pending Timing DC Any State T14S DI SSP or SP C/I= 'SSP' Test DR TIM SN0 Reset Any State DR Pin-RST or ARL C/I= 'RES' T12S SN1 EC-Training AL DR LSEC or T12E act=0 SN3 Wait for ...
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Table 29 Appearance of the State Machine to the Software C/I ind. Meaning DR LT has decided to deactivate or activation was lost: – after an activation or – after an activation attempt or – after reset ® DC ...
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A test mode is valid for 75 seconds. If during the 75 seconds a valid pulse sequence is detected the 75 s timer starts again. After expiry of the 75 s timer the MLT maintenance controller goes back to normal ...
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U-Transceiver Interrupt Structure The U-Interrupt Status register (ISTAU) contains the interrupt sources of the U- Transceiver (Figure 49). Each source can be masked by setting the corresponding bit of the U-Interrupt Mask register (MASKU) to ’1’. Such masked interrupt ...
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M56R 7 0 OPMODE.MLT MS2 MS1 + NEBE MFILT M61 CRC, TLL, M52 no Filtering M51 0 FEBE M4R MFILT 7 AIB UOA M46 CRC, TLL, M45 no M44 Filtering SCO DEA 0 ACT EOCR MFILT 15 TLL, CHG, ...
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S-Transceiver The S-Transceiver offers the NT and LT-S mode state machines described in the User’s Manual V3.4 [10]. The S-transceiver lies in IOM -2 channel 1 (default) and is configured and controlled via the registers described in but can ...
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Figure 51 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N ...
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S/Q Channels, Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Q- channel). The Q bits are defined to be ...
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The S-transceiver starts multiframing if SQXR1.MFEN is set. After multi-frame synchronization has been established in the TE, the Q data will be inserted at the upstream (TE S data will be inserted at the downstream (NT (see Table 31). Access ...
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C/I Command IOM-2 C/I Indication Figure 52 S-Transceiver Control The state diagram notation is given in The information contained in the state diagrams are: – state name – Signal received from the line interface (INFO) – Signal transmitted to ...
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IOM-2 Interface C/I code S/T Interface INFO Figure 53 State Diagram Notation As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A “ ” stands for a logical AND combination. And a ...
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C/I Codes in Reset State In the reset state the C/I code 0000 (TIM) is issued. This state is entered either after a hardware reset (RST) or with the C/I code RES. C/I Codes in Deactivated State If the S-transceiver ...
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Receive Infos on S/T I0 INFO 0 detected I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 Transmit Infos on S/T I0 INFO 0 I2 INFO 2 I4 INFO 4 It ...
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State Machine NT Mode • RST TIM RES DR Reset i0 * RES DC Any State AID RSY ARD i3*ARD G2 Lost Framing S/T i3*AID i2 i3 RSY DR ARD 2) AID RSY RSY G3 Lost Framing U i2 ...
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G1 Deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM -2 interface ...
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G4 wait for DR Final state after a deactivation request. The S-transceiver remains in this state until DC is issued. Unconditional States Test Mode TM1 Send Single Pulses Test Mode TM2 Send Continuous Pulses C/I Commands • Command Abbr. Deactivation ...
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Command Abbr. Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Receiver not RSY Synchronous Activation Request AR Illegal Code Ciolation CVR Activation Indication AI Deactivation DI Indication Data Sheet Code Remark 1110 Activation Indication Loop 1111 Deactivation ...
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State Machine LT-S Mode • RST TIM RES DR Reset i0 * RES DC Any State DC RSY ARD i3 G2 Lost Framing S ARD = AR or ARL Figure 55 State Machine LT-S ...
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G1 deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM -2 interface. G2 pending ...
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Test mode - TM2 Continuous alternating pulses are sent on the S/T-interface. • Command Abbr. Deactivation Request DR Reset RES Send Single Pulses TM1 Send Continuous TM2 Pulses Activation Request AR Activation Request ARL Loop Deactivation DC Confirmation Indication Abbr. ...
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S-Transceiver Enable / Disable The layer-1 part of the S-transceiver can be enabled/disabled with the two bits S_CONF0.DIS_TR and S_CONF2.DIS_TX. If DIS_TX=’1’ the transmit buffers are disabled. The receiver will monitor for incoming data in this configuration. By default ...
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Interrupt Structure S-Transceiver • S_STA 7 RINF 0 FECV 0 FSYN SQRR MSYN 7 MFEN 0 0 SQR1 SQR2 SQR3 0 SQR4 SQXR 7 0 MFEN 0 0 SQX1 SQX2 SQX3 0 SQX4 Figure 56 Interrupt ...
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HDLC Controller The Q-SMINT IX contains a HDLC controller which can be used for the layer-2 functions of the D- channel protocol (LAPD) or B-channel protocols. By setting the enable HDLC channel bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR ...
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Transparent mode 0 (MDS2-0 = ’110’). Characteristics: no address recognition Every received frame is stored in RFIFO (first byte after opening flag to CRC field). Additional information can be read from RSTA. Transparent mode 1 (MDS2-0 = ’111’). Characteristics: SAPI ...
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RME (Receive Message End) interrupt, indicating that the reception of one message has been completed and the message has been stored in the RFIFO. Either – a short message has been received (message length the defined block size (EXMR.RFBS) ...
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If the number of bytes in the last data block is ’0’ the length of the last received block is equal to the block size. • Table 32 Receive Byte Count with RBC11...0 in the RBCH and RBCL registers ...
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RAM EXMR.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo a receive pool full interrupt ISTAH.RPF is set. HDLC Receiver µP RAM HDLC Receiver RSTA The HDLC receiver has written further ...
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Possible Error Conditions during Reception of Frames If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTA byte will be set complete frame is lost, i.e. ...
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case of RME the last byte in RFIFO contains * the receive status information RSTA Figure 58 Data Reception Procedures Figure 59 gives an example of an interrupt controlled reception sequence, supposed that a long frame ...
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The host reads the first data block from RFIFO and acknowledges the reception by RMC. Meanwhile the second data block is received and stored in RFIFO. • The second 32 byte block is indicated by RPF which is read ...
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Figure 60 Receive Data Flow Note: The figure shows all modes except the extended transparent mode as this mode uses no typical frame structure or address recognition. Data is transferred purely transparent. Data Sheet FLAG ADDR CTRL 127 PEF ...
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The Q-SMINT IX indicates to the host that a new data block can be read from the RFIFO by means of a RPF interrupt (see previous chapter). User data is stored in the RFIFO and information about the received frame ...
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XPR (Transmit Pool Ready) interrupt, indicating that a data block bytes (block size selected via EXMR:XFBS) can be written to the XFIFO. A XPR interrupt is generated either – after a XRES (Transmitter ...
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The XFIFO requests service from the microcontroller by setting a bit in the ISTAH register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read the status register STAR (XFW, XDOV), write data in the FIFO and it ...
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Possible Error Conditions during Transmission of Frames If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly enough to a XPR interrupt, a XDU (transmit data underrun) interrupt will be raised. If the HDLC channel ...
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Command XTF Figure 61 Data Transmission Procedure The following description gives an example for the transmission byte frame with a selected block size of 32 byte (EXMR:XFBS=0): • The host writes 32 bytes to the XFIFO, ...
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As soon as the last byte of the first block is transmitted, the Q-SMINT IX issues a XPR interrupt (XFIFO space of first data block is free again) and continues transmitting the second block. • The host writes the ...
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Figure 63 Transmit Data Flow 2.6.4 Access to IOM -2 channels By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register the HDLC controller can access the D, B1, B2 channels or any combination of them ...
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If the collision detection is enabled (MODEH.DIM = ’0x1’) the stop go bit (S/G) can be used as a clear-to-send indication as in any other mode. If the S/G bit is set to ’1’ (stop) during transmission the transmitter responds ...
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CNT VALUE TIMR1 Figure 64 Timer Register 2.6.7 HDLC Controller Interrupts All interrupt sources from the ISTAH register are combined (ORed single HDLC controller interrupt signal hint. Each of ...
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MASK U ST CIC TIN WOV S MOS HDLC INT Figure 65 Interrupt Status Registers of the HDLC Controller 2.6.8 Test Function The Q-SMINT IX provides test and diagnostic functions for the HDLC controller: Digital loop via TLP (Test Loop, ...
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Reset Behavior After reset all pointers to the FIFOs are set to “0”, the XPR interrupt is set to “1” but cannot be read by the host masked, i.e. it must be unmasked so it can ...
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Operational Description 3.1 Layer 1 Activation/Deactivation 3.1.1 Complete Activation Initiated by Exchange Figure 67 depicts the procedure if activation has been initiated by the exchange side (LT). • IOM -2 TE S/T-Reference Point INFO INFO 0 ...
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Complete Activation Initiated by TE Figure 68 depicts the procedure if activation has been initiated by the terminal side (TE). • IOM -2 TE S/T-Reference Point INFO INFO 0 TIM PU AR INFO 1 INFO 2 ...
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Complete Activation Initiated by NT Figure 69 depicts the procedure if activation has been initiated by the Q-SMINT IX itself (e.g. after hook-off of a local analog phone). • IOM -2 TE S/T-Reference Point INFO 0 DC INFO 0 ...
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Complete Deactivation Figure 70 depicts the procedure if deactivation has been initiated. Deactivation of layer 1 is always initiated by the exchange. • IOM -2 TE S/T-Reference Point INFO 4 AI (AR) INFO 3 INFO 0 RSY INFO 0 ...
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Loop 2 Figure 71 depicts the procedure if loop 2 is closed and opened. • S/T-Reference Point IOM - INFO AR8/10 INFO 3 SBCX-X or IPAC-X Figure 71 Loop 2 Data Sheet NT µC ...
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Layer 1 Loopbacks Test loopbacks are specified by the national PTTs in order to facilitate the location of defect systems. Four different loopbacks are defined. The position of each loopback is illustrated in Figure 72. • ® IOM -2 ...
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In order to open an analog loopback correctly, force the U-transceiver into the RESET state. This ensures that the echo coefficients and equalizer coefficients will converge correctly when activating anew. 3.2.2 Analog Loop-Back S-Transceiver The Q-SMINT IX provides test and ...
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Loopback No.2 For loopback #2 several alternatives exist. Both the type of loopback and the location may vary. The following loopback types belong to the loopback-#2 category: • complete loopback (B1,B2,D), in the U-transceiver • complete loopback (B1,B2,D), in ...
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Loopback No.2 - Single Channel Loopbacks Single channel loopbacks are always performed directly in the U-Transceiver. No difference between the B1-channel and the B2-channel loopback control procedure exists. 3.2.4 Local Loopbacks Featured By the LOOP Register Besides the standardized ...
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LOOP.LB1=1 LOOP.LB2=1 LOOP.LBBD= 1 LOOP.U/IOM= Analog Part Digital Part Line Interface Unit DAC Echo Canceller PDM + ADC Filter Timing Recovery U-Transceiver Bandgap, Bias, Refer. Digital Part Analog Part Line Interface Unit DAC Echo Canceller PDM + ADC Filter ...
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External Circuitry 3.3.1 Power Supply Blocking Recommendation The following blocking circuitry is suggested. • VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 1) 100nF VSSD VSSD VSSa_SX VSSa_SR VSSa_UX VSSa_UR 1) These capacitors should be located as near to the pins ...
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AOUT BIN AIN BOUT Figure 77 External Circuitry U-Transceiver U-Transformer Parameters The following Table 36 lists parameters of typical U-transformers: Table 36 U-Transformer Parameters U-Transformer Parameters U-Transformer ratio; Device side : Line side Main inductance of windings on the ...
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Resistors of the External Hybrid R3, R4 and 1 1 9.5 T Resistors on the Line Side R Optional use 2x20 requires compensation resistors ...
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Table 37 S-Transformer Parameters Transformer Parameters Transformer ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line side L Coupling capacitance between the windings on the device side and ...
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Receiver The receiver of the S-transceiver is symmetrical recommended in each receive path preferable to split the resistance into two resistors for each line. This allows to place a high resistance between the transformer and the ...
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Table 38 Crystal Parameters Parameter Frequency Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components and Parasitics The load capacitance C L capacitances C (pin and PCB capacitances to ground and V Par capacitance ...
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Register Description 4.1 Address Space Figure 81 Address Space Data Sheet 7D H U-Transceiver 60 H Monitor Handler 5C H IOM -2 Handler (CDA, TSDP, CR, STI Interrupt, Global Registers 3C H S-Transceiver 30 H HDLC Controller, ...
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Interrupts Special events in the Q-SMINT IX are indicated by means of a single interrupt output, which requests the host to read status information from the Q-SMINT IX or transfer data from/to the Q-SMINT IX. Since only one INT ...
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After the Q-SMINT IX has requested an interrupt by setting its INT pin to low, the host must read first the Q-SMINT IX interrupt status register (ISTA) in the associated interrupt service routine. The INT pin of the Q-SMINT IX ...
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Register Summary r(0) = reserved, implemented as zero. HDLC Control Registers, CI Handler Name 7 6 RFIFO XFIFO ISTAH RME RPF MASKH RME RPF STAR XDOV XFW CMDR RMC RRES MODEH MDS2 MDS1 MDS0 EXMR XFBS RFBS TIMR CNT ...
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CIR0 CODR0 CIX0 CODX0 CIR1 CIX1 Data Sheet CIC0 CIC1 TBA2 TBA1 CODR1 CODX1 159 PEF 81912/81913 Register Description S/G BAS TBA0 BAC CICW CI1E CICW CI1E ...
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S-Transceiver Name DIS_ BUS CONF0 TR S_ DIS_ 0 CONF2 TX S_STA RINF S_CMD XINF SQRR MSYN MFEN SQXR 0 MFEN ISTAS 0 x MASKS MODE Data Sheet ...
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Interrupt, General Configuration Name 7 6 ISTA U ST MASK U ST MODE1 MCLK CDS MODE2 LED2 LED1 LEDC SRES 0 0 RES_ CI/TIC Data Sheet CIC TIN WOV S CIC TIN WOV ...
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IOM Handler (Timeslot, Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 CDA11 CDA20 CDA21 CDA_ DPS 0 TSDP10 CDA_ DPS 0 TSDP11 CDA_ DPS 0 TSDP20 CDA_ DPS 0 TSDP21 S_ DPS 0 TSDP_ B1 ...
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IOM Handler (Control Registers, Synchronous Transfer Interrupt Control) Name 7 6 S_CR 1 CI_CS HCI_CR DPS_ EN_ CI1 CI1 MON_ DPS EN_ CR MON SDS1_ ENS_ ENS_ CR TSS TSS+1 SDS2_ ENS_ ENS_ CR TSS TSS+1 IOM_CR SPU 0 MCDA ...
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MONITOR Handler Name 7 6 MOR MOX MOSR MDR MER MOCR MRE MRC MSTA 0 0 MCONF 0 0 Data Sheet MONITOR Receive Data MONITOR Transmit Data MDA MAB 0 0 MIE MXC ...
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Register Summary U-Transceiver Name 7 6 OPMODE 0 UCI MFILT M56 FILTER EOCR EOCW M4RMASK M4WMASK M4R verified M4 bit data of last received superframe M4W M4 bit data to be send ...
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ISTAU MLT CI MASKU MLT CI FW_ VERSION *) read back function for test use Note: Registers, which are denoted as ‘reserved‘, may not be accessed by the µC, neither for read nor for write operations. 4.4 Reset of U-Transceiver ...
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U-Transceiver Mode Register Evaluation Timing The point of time when mode settings are detected and executed differs with the mode register type. Two different behaviors can be classified: • evaluation and execution after SW-reset (C/I= RES) or upon transition ...
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Detailed HDLC Control and C/I Registers 4.6.1 RFIFO - Receive FIFO RFIFO 7 The RFIFO contains bytes of received data. After an ISTAH.RPF interrupt, a complete data block is available. The block size can be 4, ...
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ISTAH - Interrupt Status Register HDLC ISTAH Value after reset Note: The reset value cannot be read right after reset as all interrupts are masked, i.e. the XPR interrupt remains internally stored and can only be read ...
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A data block the defined block size (EXMR.XFBS) can be written to the XFIFO. A XPR interrupt will be generated in the following cases: • after a XTF or XME command as soon as the ...
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MASKH - Mask Register HDLC MASKH Value after reset RME RPF Each interrupt source in the ISTAH register can be selectively masked by setting the corresponding bit in MASKH to ‘1’. Masked interrupt status bits ...
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Data can be written in the XFIFO. This bit may be polled instead of (or in addition to) using the XPR interrupt. RACI Receiver Active Indication 0 = The HDLC receiver is not active 1 = The HDLC ...
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The Q-SMINT IX hardware timer is started (see TIMR register). XTF Transmit Transparent Frame 0 = inactive 1 = After having written bytes (EXMR.XFBS) in the XFIFO, the microcontroller initiates the transmission of ...
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MODEH - Mode Register HDLC Controller MODEH Value after reset MDS2 MDS1 MDS2-0 Mode Select Determines the message transfer mode of the HDLC controller, as follows : MDS2-0 Mode Reserved ...
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Note: SAP1, SAP2: two programmable address values for the first received address byte (in the case of an address field longer than 1 byte); SAPG = fixed value TEI1, TEI2: two programmable address values for the second ...
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Block size for the transmit FIFO data is 16 byte Note: A change of XFBS will take effect after a transmitter command (CMDR.XME, CMDR.XRES, CMDR.XTF) has been written. RFBS Receive FIFO Block Size byte 01 ...
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TIMR - Timer Register TIMR Value after reset CNT CNT CNT together with VALUE determines the time period T after which a TIN interrupt (ISTA) will be generated in the normal case: CNT=0... CNT ...
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MHA Mask High Address 0 = The high address of an incoming frame is compared with SAP1, SAP2 and SAPG The high address of an incoming frame is compared with SAP1 and SAPG. SAP1 can be masked with ...
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RBCL - Receive Frame Byte Count Low RBCL Value after reset RBC7 RBC7-0 Receive Byte Count Eight least significant bits of the total number of bytes in a received message (see RBCH register). 4.6.13 RBCH - ...
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TEI1 - TEI1 Register TEI1 Value after reset TEI1 Terminal Endpoint Identifier In all message transfer modes except for transparent modes 0, 1 and extended transparent mode, TEI1 is used by the Q-SMINT IX for address ...
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EA2 Address Field Extension Bit This bit set to ‘1’ according to HDLC/LAPD. 4.6.16 RSTA - Receive Status Register RSTA Value after reset VFR RDO VFR Valid Frame Determines whether a valid frame has ...
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SA1-0 SAPI Address Identification TA TEI Address Identification These bits are only relevant in modes with address comparison. The result of the address comparison is given by SA1-0 and TA, as follows: MDS2-0 010 (Non-Auto/8 Mode) 011 (Non-Auto/16 Mode) 111 ...
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TMH -Test Mode Register HDLC TMH Value after reset r(0) r(0) TLP Test Loop 0 = inactive 1 = The TX path of the HDLC controller is internally connected to its RX path. Data coming from ...
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A change in the received Command/Indication code has been recognized. This bit is set only when a new code is detected in two consecutive IOM-frames reset by a read of CIR0. CIC1 C/I1 Code Change 0 ...