HD6473827W Renesas Electronics Corporation., HD6473827W Datasheet
HD6473827W
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HD6473827W Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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ADE-602-142B Rev. 3 3/15/03 Hitachi Ltd. H8/3867 Series H8/3867 HD6473867, HD6433867 H8/3866 HD6433866 H8/3865 HD6433865 H8/3864 HD6433864 H8/3863 HD6433863 H8/3862 HD6433862 H8/3827 Series H8/3827 HD6473827, HD6433827 H8/3826 HD6433826 H8/3825 HD6433825 H8/3824 HD6433824 H8/3823 HD6433823 H8/3822 HD6433822 Hardware Manual The revision ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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List of Items Revised or Added for This Version Page Item 1 Table 1.1 Features / CPU 2 Table 1.1 Features / Clock pulse generators 3 Table 1.1 Features / LCD drive power supply 5 Figure 1.1 Block Diagram 8 ...
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Page Item 256 10.2.5 Serial Mode Register (SMR) / Bits 1 and 0 265 Table 10.4 Relation between n and Clock 266 Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) 267 Table 10.7 Relation between n and Clock ...
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The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3867 Series and H8/3827 Series have a system-on-a-chip ...
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Section 1 Overview.......................................................................................... 1.1 Overview............................................................................................................................ 1.2 Internal Block Diagram ..................................................................................................... 1.3 Pin Arrangement and Functions ........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ Section 2 CPU.................................................................................................. 13 2.1 Overview............................................................................................................................ 13 2.1.1 Features ................................................................................................................ 13 2.1.2 Address Space ...................................................................................................... 14 2.1.3 ...
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Memory Map ..................................................................................................................... 2.8.1 Memory Map........................................................................................................ 47 2.9 Application Notes.............................................................................................................. 53 2.9.1 Notes on Data Access........................................................................................... 2.9.2 Notes on Bit Manipulation ................................................................................... 2.9.3 Notes on Use of the EEPMOV Instruction .......................................................... 61 Section 3 Exception Handling.......................................................................... 63 3.1 Overview............................................................................................................................ ...
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Oscillator Settling Time after Standby Mode is Cleared...................................... 105 5.3.4 Standby Mode Transition and Pin States.............................................................. 106 5.4 Watch Mode ...................................................................................................................... 107 5.4.1 Transition to Watch Mode.................................................................................... 107 5.4.2 Clearing Watch Mode .......................................................................................... 107 5.4.3 Oscillator Settling Time after ...
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Register Configuration and Description............................................................... 133 8.2.3 Pin Functions........................................................................................................ 138 8.2.4 Pin States .............................................................................................................. 140 8.2.5 MOS Input Pull-Up .............................................................................................. 140 8.3 Port 3.................................................................................................................................. 141 8.3.1 Overview .............................................................................................................. 141 8.3.2 Register Configuration and Description............................................................... 141 8.3.3 Pin Functions........................................................................................................ 145 8.3.4 ...
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Overview .............................................................................................................. 171 8.10.2 Register Configuration and Description............................................................... 171 8.11 Input/Output Data Inversion Function............................................................................... 172 8.11.1 Overview .............................................................................................................. 172 8.11.2 Register Configuration and Descriptions ............................................................. 172 8.11.3 Note on Modification of Serial Port Control Register.......................................... 174 Section 9 Timers..............................................................................................175 ...
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Section 10 Serial Communication Interface ......................................................251 10.1 Overview............................................................................................................................ 251 10.1.1 Features ................................................................................................................ 251 10.1.2 Block diagram ...................................................................................................... 253 10.1.3 Pin configuration .................................................................................................. 254 10.1.4 Register configuration .......................................................................................... 254 10.2 Register Descriptions......................................................................................................... 255 10.2.1 Receive shift register (RSR)................................................................................. 255 10.2.2 Receive ...
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Pin Configuration ................................................................................................. 319 12.1.4 Register Configuration ......................................................................................... 319 12.2 Register Descriptions......................................................................................................... 320 12.2.1 A/D Result Registers (ADRRH, ADRRL)........................................................... 320 12.2.2 A/D Mode Register (AMR).................................................................................. 320 12.2.3 A/D Start Register (ADSR).................................................................................. 322 12.2.4 Clock Stop Register 1 (CKSTPR1)...................................................................... 323 ...
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H8/3867 Series and H8/3827 Series Electrical Characteristics......................................... 362 15.2.1 Power Supply Voltage and Operating Range....................................................... 362 15.2.2 DC Characteristics................................................................................................ 365 15.2.3 AC Characteristics................................................................................................ 371 15.2.4 A/D Converter Characteristics ............................................................................. 374 15.2.5 LCD Characteristics ............................................................................................. 376 15.3 Operation Timing .............................................................................................................. ...
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Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3867 Series and H8/3827 Series comprise single-chip microcomputers ...
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Table 1.1 Features Item Description CPU High-speed H8/300L CPU General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) Operating speed Instruction set compatible with H8/300 CPU Typical instructions Interrupts 36 interrupt sources 13 external interrupt ...
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Table 1.1 Features (cont) Item Description Memory Large on-chip memory H8/3862, H8/3822: 16-kbyte ROM, 1-kbyte RAM H8/3863, H8/3823: 24-kbyte ROM, 1-kbyte RAM H8/3864, H8/3824: 32-kbyte ROM, 2-kbyte RAM H8/3865, H8/3825: 40-kbyte ROM, 2-kbyte RAM H8/3866, H8/3826: 48-kbyte ROM, 2-kbyte RAM ...
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Table 1.1 Features (cont) Item Description Serial communication Two serial communication interface channels on chip interface SCI3-1: 8-bit synchronous/asynchronous serial interface Incorporates multiprocessor communication function SCI3-2: 8-bit synchronous/asynchronous serial interface Incorporates multiprocessor communication function 14-bit PWM Pulse-division PWM output for ...
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... QFP (FP-80B) — 80-pin TQFP (TFP-80C) HD6473867H, 80-pin QFP (FP-80A) HD6473827H HD6473867F, 80-pin QFP (FP-80B) HD6473827F HD6473867W, 80-pin TQFP (TFP-80C) HD6473827W ROM/RAM Size ROM 16 kbytes RAM 1 kbyte ROM 24 kbytes RAM 1 kbyte ROM 32 kbytes RAM 2 kbytes ROM 40 kbytes RAM 2 kbytes ROM 48 kbytes ...
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Internal Block Diagram Figure 1.1 shows a block diagram of the H8/3867 Series and H8/3827 Series. P1 /TMOW 0 P1 /TMOFL 1 P1 /TMOFH 2 P1 /TMIG 3 P1 /IRQ /ADTRG /IRQ /TMIC ...
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Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3867 Series and H8/3827 Series pin arrangement is shown in figures 1.2 and 1. ...
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P8 /SEG27 /SEG28 /SEG29 /SEG30/ /SEG31/ /SEG32/ /SCK 71 0 ...
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Pin Functions Table 1.2 outlines the pin functions of the H8/3864 Series. Table 1.2 Pin Functions FP-80A Type Symbol TFP-80C Power source pins ...
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Table 1.2 Pin Functions (cont) FP-80A Type Symbol TFP-80C System TEST 8 control IRQ Interrupt 72 0 IRQ pins 15 1 IRQ 16 2 IRQ 17 3 IRQ 14 4 WKP WKP 0 Timer pins ...
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Table 1.2 Pin Functions (cont) FP-80A Type Symbol TFP-80C 14-bit PWM 18 PWM pin I/O ports ...
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Table 1.2 Pin Functions (cont) FP-80A Type Symbol TFP-80C Serial RXD 22 31 communi- cation TXD 23 31 interface (SCI) SCK 21 31 RXD 70 32 TXD 71 32 SCK 69 32 A/D AN7 to An0 1 converter 80 to ...
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Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. General-register architecture ...
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Address Space The H8/300L CPU supports an address space kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure ...
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Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H ...
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Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For ...
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Data Formats The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. Bit manipulation instructions operate on 1-bit data specified as bit byte operand ( ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No. 7 1-bit data RnH 7 1-bit data RnL 7 Byte data RnH MSB ...
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Memory Data Formats Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at ...
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Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No. Address Modes 1 Register direct 2 Register indirect ...
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Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address ...
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Effective Address Calculation Table 2.2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use ...
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Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions Data transfer MOV, PUSH Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, ...
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Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag ...
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Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* MOV B/W POP W PUSH W Notes: * Size: Operand size B: Byte W: Word ...
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Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer ...
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Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Instruction Size* ADD SUB B/W ADDX SUBX B INC DEC B ADDS SUBS W DAA DAS B MULXU B DIVXU B CMP B/W NEG B Notes: * ...
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Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Instruction Size* AND XOR B NOT B Notes: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2.7 ...
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Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions Notation: op: Operation field rm, rn: Register field IMM: Immediate data ...
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Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* BSET B BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Notes: * ...
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Table 2.8 Bit-Manipulation Instructions (cont) Instruction Size* BXOR B BIXOR B BLD B BILD B BST B BIST B Notes: * Size: Operand size B: Byte Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for ...
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Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 ...
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Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont IMM ...
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Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Bcc — JMP — BSR — JSR — RTS — Function Branches to the designated address if condition ...
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Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes disp ...
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System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* RTE — SLEEP — LDC B STC B ANDC B ORC B XORC B NOP ...
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Notation: op: Operation field rn: Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code ...
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Notation: op: Operation field Figure 2.10 Block Data Transfer Instruction Code ...
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Basic Operational Timing CPU operation is synchronized by a system clock (ø subclock (ø clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø the next rising edge is ...
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Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions ...
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Three-state access to on-chip peripheral modules T ø or ø SUB Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) 44 ...
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CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt ...
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Reset state Reset occurs Program halt state 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one ...
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Memory Map 2.8.1 Memory Map The memory map of the H8/3862 and H8/3822 is shown in figure 2.16 (1), that of the H8/3863 and H8/3823 in figure 2.16 (2), that of the H8/3864 and H8/3824 in figure 2.16 (3), ...
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H'0000 H'0029 H'002A H'5FFF H'F740 H'F75F H'F780 H'FB7F H'FF90 H'FFFF Figure 2.16 (2) H8/3863 and H8/3823 Memory Map 48 Interrupt vector area On-chip ROM Not used LCD RAM (32 bytes) Not used On-chip RAM Not used Internal I/O registers (112 ...
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H'0000 Interrupt vector area H'0029 H'002A On-chip ROM H'7FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (3) H8/3864 and H8/3824 Memory Map ...
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H'0000 H'0029 H'002A H'9FFF H'F740 H'F75F H'F780 H'FF7F H'FF90 H'FFFF Figure 2.16 (4) H8/3865 and H8/3825 Memory Map 50 Interrupt vector area On-chip ROM Not used LCD RAM (32 bytes) Not used On-chip RAM Not used Internal I/O registers (112 ...
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H'0000 Interrupt vector area H'0029 H'002A On-chip ROM H'BFFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (5) H8/3866 and H8/3826 Memory Map ...
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H'0000 H'0029 H'002A H'EDFF H'F740 H'F75F H'F780 H'FF7F H'FF90 H'FFFF Figure 2.16 (6) H8/3867 and H8/3827 Memory Map 52 Interrupt vector area On-chip ROM Not used LCD RAM (32 bytes) Not used On-chip RAM Not used Internal I/O registers (112 ...
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Application Notes 2.9.1 Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas ...
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H'0000 Interrupt vector area (42 bytes) H'0029 H'002A On-chip ROM 1 * H'7FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 On-chip RAM 2 H'FF7F* Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Notes: The example ...
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Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers ...
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Example 2: BSET instruction executed designating port 3 P3 and P3 are designated as input pins, with a low-level signal input signal The remaining pins example, the BSET instruction is used ...
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Prior to executing BSET] MOV. B #80, R0L MOV. B R0L, @RAM0 MOV. B R0L, @PDR3 Input/output Input Input Pin state Low level High level Low level Low level Low level Low level Low level ...
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Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P3 high-level signal The remaining pins signals. In this ...
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Prior to executing BCLR] MOV. B #3F, R0L MOV. B R0L, @RAM0 MOV. B R0L, @PCR3 Input/output Input Input Pin state Low level High level Low level Low level Low level Low level Low level ...
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Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers that contain write-only bits. Table 2.12 Registers with Shared Addresses Register Name Timer counter and timer load register C Port data register 1* Port ...
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Notes on Use of the EEPMOV Instruction The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified the address specified by R6 ...
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62 ...
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Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3864 Series when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority ...
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When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input. RES ø Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) ...
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Interrupt Immediately after Reset After a reset interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent ...
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Table 3.2 Interrupt Sources and Their Priorities Interrupt Source Interrupt RES Reset IRQ IRQ 0 0 IRQ IRQ 1 1 IRQ IRQ 2 2 IRQ IRQ 3 3 IRQ IRQ 4 4 WKP WKP 0 0 WKP WKP 1 1 ...
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Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt request register 1 Interrupt request register 2 Wakeup interrupt ...
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Bit 3: IRQ edge select (IEG3) 3 Bit 3 selects the input sensing of the IRQ Bit 3 IEG3 Description Falling edge of IRQ 0 Rising edge of IRQ 1 Bit 2: IRQ edge select (IEG2) 2 Bit 2 selects ...
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Interrupt enable register 1 (IENR1) Bit 7 IENTA Initial value 0 Read/Write R/W IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Timer A interrupt enable (IENTA) Bit 7 enables or disables timer A ...
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Interrupt enable register 2 (IENR2) Bit 7 IENDT IENAD Initial value 0 Read/Write R/W IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Direct transfer interrupt enable (IENDT) Bit 7 enables or disables direct ...
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Bit 3: Timer FH interrupt enable (IENTFH) Bit 3 enables or disables timer FH compare match and overflow interrupt requests. Bit 3 IENTFH Description 0 Disables timer FH interrupt requests 1 Enables timer FH interrupt requests Bit 2: Timer FL ...
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Interrupt request register 1 (IRR1) Bit 7 IRRTA Initial value 0 * Read/Write R/W Note: * Only a write of 0 for flag clearing is possible IRR1 is an 8-bit read/write register, in which a corresponding flag is set ...
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Interrupt request register 2 (IRR2) Bit 7 IRRDT IRRAD Initial value 0 * Read/Write R/W Note: * Only a write of 0 for flag clearing is possible IRR2 is an 8-bit read/write register, in which a corresponding flag is ...
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Bit 4: Timer G interrupt request flag (IRRTG) Bit 4 IRRTG Description 0 Clearing conditions: When IRRTG = cleared by writing 0 1 Setting conditions: When the TMIG pin is designated for TMIG input and the designated ...
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Bit 0: Asynchronous event counter interrupt request flag (IRREC) Bit 0 IRREC Description 0 Clearing conditions: When IRREC = cleared by writing 0 1 Setting conditions: When ECH overflows in 16-bit counter mode, or ECH or ECL ...
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Wakeup Edge Select Register (WEGR) Bit 7 WKEGS7 WKEGS6 Initial value 0 Read/Write R/W WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn. WEGR is initialized to H' reset. Bit ...
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Interrupts IRQ to IRQ 4 0 are requested by input signals to pins IRQ Interrupts IRQ to IRQ 4 0 detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG4 to IEG0 ...
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Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. External or internal interrupts External interrupts or internal interrupt enable signals ...
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If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value pushed onto ...
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Program execution state IRRI0 = 1 Yes IEN0 = 1 Yes Yes PC contents saved CCR contents saved I 1 Branch to interrupt handling routine Notation: PC: Program counter CCR: Condition code register I: I bit of ...
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SP – – – – (R7) Stack area Prior to start of interrupt exception handling Notation Upper 8 bits of program counter (PC Lower 8 bits of ...
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Figure 3.5 Interrupt Sequence ...
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Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item Waiting time for completion of ...
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Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3864 Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so ...
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Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port ...
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Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the ...
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Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator ...
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System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator providing external clock input. 1. Connecting a crystal oscillator Figure 4.2 shows a typical method of ...
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Connecting a ceramic oscillator Figure 4.4 shows a typical method of connecting a ceramic oscillator OSC OSC Figure 4.4 Typical Connection to Ceramic Oscillator 3. Notes on board design When generating ...
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External clock input method Connect an external clock signal to pin OSC typical connection. OSC 1 OSC 2 Figure 4.6 External Clock Input (Example) Frequency Duty cycle Note: The circuit parameters above are recommended by the crystal or ceramic ...
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Subclock Generator 1. Connecting a 32.768-kHz/38.4 kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz/38.4 kHz crystal oscillator, as shown in figure 4.7. Follow the same precautions as noted under 3. notes ...
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Pin connection when not using subclock When the subclock is not used, connect pin X figure 4.9. Figure 4.9 Pin Connection when not Using Subclock 3. External clock input Connect the external clock to the X1 pin and leave ...
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Prescalers The H8/3864 Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler 13-bit counter using the system clock (ø) as its input clock. Its prescaled outputs provide internal ...
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Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTAT™ versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending ...
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Section 5 Power-Down Modes 5.1 Overview The H8/3864 Series has nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the eight operating modes. Table ...
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Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal states in each mode. Reset state Program halt state Standby mode *4 *1 instruction Watch mode Mode Transition Conditions (1) LSON MSON SSBY TMA3 a 0 ...
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Table 5.2 Internal State in Each Operating Mode Active Mode High- Function Speed System clock oscillator Functions Functions Functions Functions Halted Subclock oscillator Functions Functions Functions Functions Functions CPU Instructions Functions Functions Halted operations RAM Registers I/O ports External IRQ ...
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System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Registers Name System control register 1 System control register 2 1. System control register 1 (SYSCR1) Bit 7 ...
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Bits Standby timer select (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due ...
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Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0) Bits 1 and 0 choose ø /128, ø osc speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high- speed) mode or subactive mode. ...
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Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after ...
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Bits 1 and 0: Subactive mode clock select (SA1 and SA0) These bits select the CPU clock rate (ø cannot be modified in subactive mode. Bit 1 Bit 0 SA1 SA0 Description 0 0 ø ø ...
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Sleep Mode 5.2.1 Transition to Sleep Mode 1. Transition to sleep (high-speed) mode The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared ...
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Clock Frequency in Sleep (Medium-Speed) Mode Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1. 5.3 Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode ...
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Oscillator Settling Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. • When a crystal oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to ...
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Standby Mode Transition and Pin States When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit SSBY is set to 1 and bit LSON is cleared SYSCR1, and bit TMA3 ...
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Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA ...
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Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to ...
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Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ WKP interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep ...
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Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared ...
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Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program ...
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Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, ...
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Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON ...
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Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and ...
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Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock ...
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Table 5.5 (cont) Register Name Bit Name CKSTPR2 LDCKSTP PWCKSTP WDCKSTP AECKSTP Note: For details of module operation, see the sections on the individual modules. 116 Operation 1 LCD module standby mode is cleared 0 LCD is set to module ...
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Overview The H8/3862 and H8/3822 have 16 kbytes of on-chip mask ROM, the H8/3863 and H8/3823 have 24 kbytes, the H8/3864 and H8/3824 have 32 kbytes, the H8/3865 and H8/3825 have 40 kbytes, the H8/3866 and H8/3826 have 48 ...
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H8/3867 and H8/3827 PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as ...
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H8/3867 and H8/3827 FP-80A, TFP-80C FP-80B ...
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Address in MCU mode Note: * The output data is not guaranteed if this address area is read in PROM mode. There- fore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If programming ...
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H8/3867 and H8/3827 Programming The write, verify, and other modes are selected as shown in table 6.3 in H8/3867 and H8/3827 PROM mode. Table 6.3 Mode Selection in PROM Mode (H8/3867, H8/3827 Mode Write L H Verify ...
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Yes Error Figure 6.4 High-Speed, High-Reliability Programming Flow Chart 122 Start Set write/verify mode V = 6 Address = Write ...
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Table 6.4 and table 6.5 give the electrical characteristics in programming mode. Table 6.4 DC Characteristics (Conditions 6.0 V ±0. Item Input high OE, CE, PGM level voltage ...
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Table 6.5 AC Characteristics (Conditions 6.0 V ±0. Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time V setup time PP Programming pulse width ...
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Figure 6.5 shows a PROM write/verify timing diagram. Address t AS Data Input data VPS VCS CES PGM ...
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Programming Precautions Use the specified programming voltage and timing. The programming voltage in PROM mode (V permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 ...
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Reliability of Programmed Data A highly effective way to improve data retention characteristics is to bake the programmed chips at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early ...
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128 ...
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Overview The H8/3862, H8/3863, H8/3822, and H8/3823 have 1 kbyte of high-speed static RAM on-chip, and the H8/3864, H8/3865, H8/3866, H8/3867, H8/3824, H8/3825, H8/3826, and H8/3827 have 2 kbytes. The RAM is connected to the CPU by a 16-bit ...
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130 ...
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Overview The H8/3864 Series is provided with six 8-bit I/O ports, one 4-bit I/O port, one 3-bit I/O port, one 8-bit input-only port, and one 1-bit input-only port. Table 8.1 indicates the functions of each port. Each port has ...
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Table 8.1 Port Functions (cont) Port Description Port 4 1-bit input port 3-bit I/O port Port 5 8-bit I/O port MOS input pull-up option Port 6 8-bit I/O port MOS input pull-up option Port 7 8-bit I/O port Port 8 ...
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Port 1 8.2.1 Overview Port 8-bit I/O port. Figure 8.1 shows its pin configuration. 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Port data register ...
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Port data register 1 (PDR1) Bit Initial value 0 Read/Write R/W PDR1 is an 8-bit register that stores data for port 1 pins P1 bits are set to 1, the values stored in PDR1 are read, ...
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Port pull-up control register 1 (PUCR1) Bit 7 PUCR1 PUCR1 7 Initial value 0 Read/Write R/W PUCR1 controls whether the MOS pull-up of each of the port 1 pins P1 a PCR1 bit is cleared to 0, setting the ...
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Bit 6: P1 /IRQ pin function switch (IRQ2 This bit selects whether pin P1 Bit 6 IRQ2 Description 0 Functions as P1 Functions as IRQ 1 Note: Rising or falling edge sensing can be designated for IRQ Bit ...
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Bit 2: P1 /TMOFH pin function switch (TMOFH) 2 This bit selects whether pin P1 Bit 2 TMOFH Description 0 Functions Functions as TMOFH output pin Bit 1: P1 /TMOFL pin function switch (TMOFL) 1 This bit ...
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Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Pin Functions and Selection Method P1 /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in ...
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Table 8.3 Port 1 Pin Functions (cont) Pin Pin Functions and Selection Method P1 /TMIG The pin function depends on bit TMIG in PMR1 and bit PCR1 3 TMIG PCR1 Pin function P1 /TMOFH The pin function depends on bit ...
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Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset P1 /IRQ /TMIF High /IRQ impedance /IRQ /TMIC ...
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Port 3 8.3.1 Overview Port 8-bit I/O port, configured as shown in figure 8.2. 8.3.2 Register Configuration and Description Table 8.5 shows the port 3 register configuration. Table 8.5 Port 3 Registers Name Port data register ...
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Port data register 3 (PDR3) Bit Initial value 0 Read/Write R/W PDR3 is an 8-bit register that stores data for port 3 pins P3 bits are set to 1, the values stored in PDR3 are read, ...
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Port mode register 3 (PMR3) Bit 7 AEVL AEVH Initial value 0 Read/Write R/W PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'04. Bit 7: ...
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Bit 4: TMIG noise canceler select (NCS) This bit controls the noise canceler for the input capture input signal (TMIG). Bit 4 NCS Description 0 Noise cancellation function not used 1 Noise cancellation function used Bit 3: P4 /IRQ pin ...
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Bit 0: P3 /PWM pin function switch (PWM) 0 This bit selects whether pin P3 Bit 0 PWM Description 0 Functions Functions as PWM output pin 8.3.3 Pin Functions Table 8.9 shows the port 3 pin functions. ...
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Table 8.9 Port 3 Pin Functions (cont) Pin Pin Functions and Selection Method P3 /RXD The pin function depends on bit RE in SCR3-1 and bit PCR3 PCR3 Pin function P3 /SCK The pin function depends on ...
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Pin States Table 8.10 shows the port 3 pin states in each operating mode. Table 8.10 Port 3 Pin States Pins Reset P3 /AEVL High /AEVH impedance 6 P3 /TXD /RXD ...
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Port 4 8.4.1 Overview Port 3-bit I/O port and 1-bit input port, configured as shown in figure 8.3. 8.4.2 Register Configuration and Description Table 8.8 shows the port 4 register configuration. Table 8.8 Port 4 Registers ...
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Port control register 4 (PCR4) Bit 7 — Initial value 1 Read/Write — PCR4 is an 8-bit register for controlling whether each of port 4 pins P4 input pin or output pin. Setting a PCR4 bit to 1 makes ...
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Table 8.9 Port 4 Pin Functions (cont) Pin Pin Functions and Selection Method P4 /SCK The pin function depends on bit CKE1 and CKE0 in SCR3-2, bit COM32 SMR32, and bit PCR4 CKE1 CKE0 COM32 PCR4 Pin ...
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Port 5 8.5.1 Overview Port 8-bit I/O port, configured as shown in figure 8.4. 8.5.2 Register Configuration and Description Table 8.11 shows the port 5 register configuration. Table 8.11 Port 5 Registers Name Port data register ...
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Port data register 5 (PDR5) Bit Initial value 0 Read/Write R/W PDR5 is an 8-bit register that stores data for port 5 pins P5 bits are set to 1, the values stored in PDR5 are read, ...
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Port mode register 5 (PMR5) Bit 7 WKP WKP 7 Initial value 0 Read/Write R/W PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit ...
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Pin Functions Table 8.12 shows the port 5 pin functions. Table 8.12 Port 5 Pin Functions Pin Pin Functions and Selection Method P5 /WKP / The pin function depends on bit WKP 7 7 SEG to SGS3 to SGS0 ...
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MOS Input Pull-Up Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for ...
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Port 6 8.6.1 Overview Port 8-bit I/O port. The port 6 pin configuration is shown in figure 8.5. 8.6.2 Register Configuration and Description Table 8.14 shows the port 6 register configuration. Table 8.14 Port 6 Registers ...
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Port data register 6 (PDR6) Bit Initial value 0 Read/Write R/W PDR6 is an 8-bit register that stores data for port 6 pins P6 If port 6 is read while PCR6 bits are set to 1, ...
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Port pull-up control register 6 (PUCR6) Bit 7 PUCR6 PUCR6 7 Initial value 0 Read/Write R/W PUCR6 controls whether the MOS pull-up of each of the port 6 pins P6 a PCR6 bit is cleared to 0, setting the ...
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MOS Input Pull-Up Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that ...
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Port 7 8.7.1 Overview Port 8-bit I/O port, configured as shown in figure 8.6. 8.7.2 Register Configuration and Description Table 8.17 shows the port 7 register configuration. Table 8.17 Port 7 Registers Name Port data register ...
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Port data register 7 (PDR7) Bit Initial value 0 Read/Write R/W PDR7 is an 8-bit register that stores data for port 7 pins P7 bits are set to 1, the values stored in PDR7 are read, ...
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Pin Functions Table 8.18 shows the port 7 pin functions. Table 8.18 Port 7 Pin Functions Pin Pin Functions and Selection Method P7 /SEG to The pin function depends on bit PCR7 /SEG LPCR ...
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Port 8 8.8.1 Overview Port 8-bit I/O port configured as shown in figure 8.7. 8.8.2 Register Configuration and Description Table 8.20 shows the port 8 register configuration. Table 8.20 Port 8 Registers Name Port data register ...
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Port data register 8 (PDR8) Bit Initial value 0 Read/Write R/W PDR8 is an 8-bit register that stores data for port 8 pins P8 bits are set to 1, the values stored in PDR8 are read, ...
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Pin Functions Table 8.21 shows the port 8 pin functions. Table 8.21 Port 8 Pin Functions Pin Pin Functions and Selection Method P8 /SEG / The pin function depends on bit PCR8 LPCR. 1 SEGS3 ...
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Pin States Table 8.22 shows the port 8 pin states in each operating mode. Table 8.22 Port 8 Pin States Pins Reset P8 /SEG /CL High /SEG /CL impedance /SEG /DO ...
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Port A 8.9.1 Overview Port 4-bit I/O port, configured as shown in figure 8.8. 8.9.2 Register Configuration and Description Table 8.23 shows the port A register configuration. Table 8.23 Port A Registers Name Port data register ...
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Port control register A (PCRA) Bit 7 — Initial value 1 Read/Write — PCRA controls whether each of port A pins PA Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit ...
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Pin Functions Table 8.24 shows the port A pin functions. Table 8.24 Port A Pin Functions Pin Pin Functions and Selection Method PA /COM The pin function depends on bit PCRA 3 4 SEGS3 to SEGS0 PCRA Pin function ...
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Pin States Table 8.25 shows the port A pin states in each operating mode. Table 8.25 Port A Pin States Pins Reset PA /COM High /COM impedance /COM /COM 0 ...
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Port B 8.10.1 Overview Port 8-bit input-only port, configured as shown in figure 8.9. 8.10.2 Register Configuration and Description Table 8.26 shows the port B register configuration. Table 8.26 Port B Register Name Port data register ...
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Input/Output Data Inversion Function 8.11.1 Overview With input pins WKP to WKP 0 data can be handled in inverted form. P3 /RXD 4 P4 /RXD 1 P3 /TXD 5 P4 /TXD 2 Figure 8.10 Input/Output Data Inversion Function 8.11.2 ...
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Bit 0: RXD pin input data inversion switch 31 Bit 0 specifies whether or not RXD Bit 0 SCINV0 Description 0 RXD input data is not inverted 31 1 RXD input data is inverted 31 Bit 1: TXD pin output ...
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Bit 4: P3 /TXD pin function switch (SPC31 This bit selects whether pin P3 Bit 4 SPC31 Description 0 Functions Functions as TXD Note: * Set the TE bit in SCR3 after setting this bit ...
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Overview The H8/3864 Series provides six timers: timers and a watchdog timer, and an asynchronous event counter. The functions of these timers are outlined in table 9.1. Table 9.1 Timer Functions Name Functions Timer A ...
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Table 9.1 Timer Functions (cont) Name Functions Watchdog Reset signal timer generated when8- bit counter overflows Asynchro- 16-bit counter nous Also usable as two event independent 8-bit counter counters Counts events asynchronous to ø and øw 176 Event Internal Clock ...
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Timer A 9.2.1 Overview Timer 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz, from ...
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Block diagram Figure 9.1 shows a block diagram of timer A. ø W 1/4 ø ø /32 W ø /16 W ø ø TMOW ø/32 ø/16 ø/8 ø/4 ø Notation: TMA: Timer mode ...
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Register configuration Table 9.3 shows the register configuration of timer A. Table 9.3 Timer A Registers Name Timer mode register A Timer counter A Clock stop register 1 Subclock output select register 9.2.2 Register Descriptions 1. Timer mode register ...
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Bits Clock output select (TMA7 to TMA5) Bits choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16 can be output in ...
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Bits Internal clock select (TMA3 to TMA0) Bits select the clock input to TCA. The selection is made as follows. Bit 3 Bit 2 Bit 1 TMA3 TMA2 TMA1 ...
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Timer counter A (TCA) Bit 7 TCA7 TCA6 Initial value 0 Read/Write R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 ...
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Subclock Output Select Register (CWOSR) Bit — — Initial value Read/Write CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin. CWOSR is initialized to H'FE by ...
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Real-time clock time base operation When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set ...
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Timer C 9.3.1 Overview Timer 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer C are given below. Choice ...