CY7C1380C-167BGC Cypress Semiconductor Corporation., CY7C1380C-167BGC Datasheet
CY7C1380C-167BGC
Related parts for CY7C1380C-167BGC
CY7C1380C-167BGC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05237 Rev. *D Functional Description The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The ...
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... Logic Block Diagram – CY7C1380C (512K x 36) A0, A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP DQ DQP BYTE BW D WRITE REGISTER DQ DQP BYTE BW C WRITE REGISTER DQ DQP BYTE BW B WRITE REGISTER DQ DQP BYTE BW A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL 2 Logic Block Diagram – ...
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... Document #: 38-05237 Rev. *D 100-pin TQFP Pinout DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1380C CY7C1382C DDQ V 76 SSQ DQP SSQ 70 V DDQ CY7C1382C ( DDQ V 60 SSQ SSQ V 54 DDQ Page ...
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... Pin Configurations (continued DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ 72M U V DDQ Document #: 38-05237 Rev. *D 119-ball BGA (1 Chip Enable with JTAG) CY7C1380C (512K x 36 ADSP A A ADSC DQP ADV CLK BWE DQP MODE 72M TMS TDI TCK TDO ...
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... DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M 288M CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05237 Rev. *D 165-ball fBGA CY7C1380C (512K x 36 BWE CLK TDI A1 TDO TCK TMS CY7C1382C (1M x 18) ...
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... CY7C1380C–Pin Definitions Name TQFP BGA 37,36,32, P4,N4 33,34,35, A2,B2, 42,43,44,45, C2,R2, 46,47,48, A3,B3,C3, 49,50,81, T3,T4,A5,B5, 82,99,100 C5, T5,A6,B6,C6, 93,94,95, L5,G5 G3, BWE CLK [ [ ADV Document #: 38-05237 Rev. *D fBGA I/O R6,P6,A2, Input- A10,B2, Synchronous B10,N6,P3,P4, P8,P9,P10, P11,R3,R4,R8, R9,R10,R11 R6 B5,A5,A4, Input- B4 Synchronous H4 B7 Input- ...
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... CY7C1380C–Pin Definitions (continued) Name TQFP BGA 84 ADSP 85 ADSC ZZ 64 52,53,56, K6,L6, DQs, DQPs 57,58,59, M6,N6, 62,63,68, K7,L7, 69,72,73, N7,P7, 74,75,78, E6,F6, 79,2,3,6,7,8,9, G6,H6, 12,13,18,19,22 D7,E7, , G7,H7, 23,24,25, D1,E1, 28,29,51, G1,H1, 80,1,30 E2,F2, G2,H2, K1,L1, N1,P1, K2,L2, M2,N2, P6,D6, D2,P2 V 15,41,65, ...
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... CY7C1380C–Pin Definitions (continued) Name TQFP BGA V 5,10,21,26,55, SSQ 60,71 4,11,20,27,54, A1,F1,J1,M1, DDQ 61,70, U1, 77 A7,F7,J7,M7, MODE 31 TDO - TDI - TMS - TCK - NC 14,16,66, B1,C1, 39,38 R1,T1,T2,J3, D4, L4,J5,R5,6T, 6U, B7,C7, Document #: 38-05237 Rev. *D fBGA I I/O Ground C3,C9,D3,D9, I/O Power E3,E9,F3,F9,G Supply 3, U7 G9,J3,J9, K3,K9,L3, ...
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... A9 Input- Advance Input signal, sampled on the rising Synchronous edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. CY7C1380C CY7C1382C Description are sampled active. A1: A0 are fed 3 and BWE select/deselect the device. ADSP HIGH ...
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... Power Supply Power supply inputs to the core of the device. F4,F8, G4,G8,H4, H8,J4,J8, K4,K8,L4, L8,M4,M8 H2,C4,C5,C6, Ground Ground for the core of the device. C7,C8,D5,D6, D7,E5,E6,E7, F5,F6,F7, G5,G6,G7, H5,H6,H7,J5,J 6,J7, K5,K6,K7, L5,L6,L7, M5,M6,M7,N4 I/O Ground Ground for the I/O circuitry. CY7C1380C CY7C1382C Description is deasserted HIGH. 1 are placed in a tri-state condition. Page ...
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... V packages. A5,B1,B4 Connects. Not internally connected to the die. C1,C2,C10,D1 ,D10, E1,E10,F1, F10,G1, G10,H1,H3,H9 ,H10,J2,J11, K2, K11,L2,L1,M2, M11, N2,N10,N5,N7 N11,P1,A1, B11, P2,R2 CY7C1380C CY7C1382C Description or left DD . This pin is not available on TQFP packages. . This pin is not available on TQFP SS Page ...
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... Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1380C is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE ...
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... CY7C1380C CY7C1382C , ADSP, and ADSC must after the ZZ input ZZREC Min. Max. Unit 60mA CYC 2t ns CYC 2t ns CYC 0 ns ADV WRITE OE CLK L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State Tri-State L L-H Tri-State L L L-H Tri-State L L-H Tri-State ...
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... OE is asynchronous and is not sampled with the clock rise masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW) . [5] Truth Table for Read/Write Function (CY7C1380C) Read Read Write Byte A – ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380C incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... CLK captured in the boundary scan register. Once the data is captured possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. CY7C1380C CY7C1382C Unlike the SAMPLE/PRELOAD ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE Symbol /t = 1ns CY7C1380C CY7C1382C TDOV t TDOX UNDEFINED [9, 10] Min Max t 100 TCYC ...
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... OL DDQ V = 2.5V DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1380C CY7C1382C V to 2.5V SS 1.25V 50Ω 50Ω 20pF O MIN MAX UNITS 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 ...
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... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1380C CY7C1382C DESCRIPTION Describes the version number. Reserved for Internal Use ...
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... BGA Boundary Scan Order BIT# BALL Document #: 38-05237 Rev. *D CY7C1380C (512K x 36) BIT Not Bonded (Preset CY7C1380C CY7C1382C BALL Internal Internal Page ...
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... Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset CY7C1380C CY7C1382C BALL Internal Internal G3 L5 Internal Page ...
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... Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL B10 9 A10 10 C11 11 E10 12 F10 13 G10 14 D10 15 D11 16 E11 17 F11 18 G11 19 H11 20 J10 21 K10 22 L10 23 M10 24 J11 25 K11 26 L11 27 M11 28 N11 29 R11 30 R10 P10 P11 Document #: 38-05237 Rev. *D BIT# BALL ID 37 ...
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... CY7C1382C (1M x 18) BIT Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset CY7C1380C CY7C1382C BALL Internal Page ...
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... CYC 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz 7.5-ns cycle, 133 MHz V = Max, Device Deselected, All speeds 0. > V – 0.3V DDQ CY7C1380C CY7C1382C Ambient Temperature 0°C to +70°C 3.3V– 5%/+10% 2.5V – -40° +85°C Min. Max. 3.135 3.6 3.135 ...
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... During this time V < Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51. Test Conditions Package T = 25qC MHz 3.3V 2.5V DDQ CY7C1380C CY7C1382C Min. Max. 105 100 /2). CYC and V < DDQ DD\ TQFP BGA fBGA ...
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... L (a) Document #: 38-05237 Rev 317: 3.3V OUTPUT 351: INCLUDING JIG AND (b) SCOPE R = 1667: 2.5V V OUTPUT =1538: INCLUDING JIG AND (b) SCOPE CY7C1380C CY7C1382C ALL INPUT PULSES V DD 90% 90% 10% GND d 1ns (c) ALL INPUT PULSES DD 90% 90% 10% GND d 1ns (c) Page 10% d 1ns 10% ...
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... V is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1380C CY7C1382C 200 MHz 167 MHz 133 MHz Min. Max Min. Max ...
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... OEV OEHZ t OELZ t DOH Q(A1) Q(A2) Q( DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH LOW. X CY7C1380C CY7C1382C A3 Burst continued with new base address Deselect cycle t CHZ Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ is HIGH LOW HIGH ...
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... OEHZ Data Out (Q) BURST READ Single WRITE Document #: 38-05237 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED CY7C1380C CY7C1382C ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVS ADVH D( D(A3 Extended BURST WRITE ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC . 24 HIGH. Document #: 38-05237 Rev WES t WEH OELZ D(A3) t OEHZ Q(A4) Single WRITE DON’T CARE UNDEFINED CY7C1380C CY7C1382C A5 D(A5) D(A6) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs Page ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 26. DQs are in high-Z when exiting ZZ sleep mode Document #: 38-05237 Rev ZZI I DDZZ High-Z DON’T CARE CY7C1380C CY7C1382C t ZZREC t RZZI DESELECT or READ Only Page ...
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... CY7C1380C-225BGC CY7C1382C-225BGC CY7C1380C-225BZC CY7C1382C-225BZC 200 CY7C1380C-200AC CY7C1382C-200AC CY7C1380C-200BGC CY7C1382C-200BGC CY7C1380C-200BZC CY7C1382C-200BZC 167 CY7C1380C-167AC CY7C1382C-167AC CY7C1380C-167BGC CY7C1382C-167BGC CY7C1380C-167BZC CY7C1382C-167BZC 133 CY7C1380C-133AC 167 CY7C1380C-167AI CY7C1382C-167AI CY7C1380C-167BGI CY7C1382C-167BGI CY7C1380C-167BZI CY7C1382C-167BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. DIMENSIONS ARE IN MILLIMETERS 0.30±0.08 0.65 TYP STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. A CY7C1380C CY7C1382C 1.40±0.05 12°±1° A SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. 51-85050-*A Page ...
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... Package Diagrams (continued) Document #: 38-05237 Rev. *D 119-Lead PBGA ( 2.4 mm) BG119 CY7C1380C CY7C1382C 51-85115-*B Page ...
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... FBGA ( 1.2 mm) BB165A i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05237 Rev. *D CY7C1380C CY7C1382C 51-85122-*C Page ...
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... Document History Page Document Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05237 REV. ECN NO. Issue Date ** 116277 08/27/02 *A 121540 11/21/02 *B 121797 11/21/02 *C 128904 09/11/03 *D 206081 02/13/04 Document #: 38-05237 Rev. *D Orig. of Change Description of Change SKX New Data Sheet DSG Updated package diagrams 51-85115 (BG119) to rev ...