CY62126V-55ZC Cypress Semiconductor Corporation., CY62126V-55ZC Datasheet

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CY62126V-55ZC

Manufacturer Part Number
CY62126V-55ZC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY62126V-55ZC

Case
TSSOP-44L
Features
Functional Description
The CY62126V is a high-performance CMOS static RAM or-
ganized as 65,536 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption by 99% when deselected. The device enters
power-down mode when CE is HIGH.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
Cypress Semiconductor Corporation
• 2.7V–3.6V operation
• CMOS for optimum speed/power
• Low active power (70 ns)
• Low standby power (70 ns, LL version)
• Automatic power-down when deselected
• Independent control of Upper and Lower Bytes
• Available in 44-pin TSOP II (forward)
A
A
A
Logic Block Diagram
A
A
A
A
A
A
A
12
11
10
— 198 mW (max.) (55 mA)
— 54 W (max.) (15 A)
1
0
9
7
6
3
2
COLUMN DECODER
DATA IN DRIVERS
1024 X 1024
RAM Array
64K x 16
3901 North First Street
PRELIMINARY
I/O
I/O
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
I/O pins (I/O
fied on the address pins (A
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
data from memory will appear on I/O
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY62126V is available in standard 44-pin TSOP Type II
(forward pinout) and mini-BGA packages.
1
9
– I/O
– I/O
BHE
WE
CE
OE
BLE
62126V–1
8
16
15
). If byte high enable (BHE) is LOW, then data from
San Jose
9
1
through I/O
to I/O
64K x 16 Static RAM
8
. If byte high enable (BHE) is LOW, then
Pin Configurations
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
V
WE
A
A
A
A
NC
CE
CC
A
A
A
A
A
SS
16
15
14
13
12
TSOP II (Forward)
4
3
2
1
0
1
2
3
4
5
6
7
8
0
1
) is written into the location speci-
through A
CA 95134
through I/O
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
Top View
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
15
to I/O
).
62126V–2
16
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
NC
A
A
A
A
NC
CY62126V
February 13, 1998
) are placed in a
1
5
6
7
SS
CC
8
9
10
11
16
16
15
14
13
12
11
10
9
through I/O
. See the truth
408-943-2600
8
), is
0

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CY62126V-55ZC Summary of contents

Page 1

... HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY62126V is available in standard 44-pin TSOP Type II (forward pinout) and mini-BGA packages. I/O – I/O ...

Page 2

... Com’l LL Ind’l LL Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range [1] .... –0.5V to +4.6V Range Commercial +0.5V CC Industrial +0. CY62126V 62126V–3 62126V-55 62126V- 0.3 0 Ambient [2] Temperature +70 C 2.7V–3.6V – +85 C Units ...

Page 3

... MAX Max – 0.3V – 0.3V 0.3V, f=0 Com’l IN Ind’l Test Conditions MHz 3. 1076 3.0V 3. GND 1262 <3 ns (b) 581 1.62V 3 CY62126V 62126V [3] Min. Typ. Max. Unit 2.2 0.4 2 0.3 –0.3 0.4 –1 +1 – 0 0.5 30 Max. Unit ...

Page 4

... The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Refer to truth table for further conditions from BHE and BLE. PRELIMINARY Description [7] [6,7] is less than less than HZCE LZCE HZOE LZOE HZWE 4 CY62126V 62126V–55 62126V–70 Min. Max. Min. Max ...

Page 5

... CC Com’ – 0.3V or Ind’ 0.3V IN DATA RETENTION MODE 3.0V V > CDR OHA DBE t DOE DATA VALID 50 CY62126V Min. Typ Max. Unit 2.0 3 62126V–5 DATA VALID 62126V-6 t HZBE t HZOE t HIGH HZCE IMPEDANCE t PD ICC 50% ...

Page 6

... If CE, BHE, or BLE go HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. During this period the I/Os are in the output state and input signals should not be applied. PRELIMINARY SCE PWE t SD DATA VALID [13,14 SCE PWE DATA VALID IN 6 CY62126V 62126V 62126V-9 ...

Page 7

... Data Out Read All bits High Z Read Lower bits only Data Out Read Upper bits only Data In Write All bits High Z Write Lower bits only Data In Write Upper bits only High Z Selected, Outputs Disabled 7 CY62126V LZWE 62126V-10 Mode Power Standby ( Active (I ) ...

Page 8

... Ordering Information Speed (ns) Ordering Code 55 CY62126V-55ZC CY62126VL-55ZC CY62126VLL-55ZC CY62126VLL-55ZI 55 CY62126V-55BAC CY62126VL-55BAC CY62126VLL-55BAC CY62126VLL-55BAI 70 CY62126V-70ZC CY62126VL-70ZC CY62126VLL-70ZC CY62126VLL-70ZI 70 CY62126V-70BAC CY62126VL-70BAC CY62126VLL-70BAC CY62126VLL-70BAI Shaded area contains advanced information. Document #: 38–00584 Package Diagrams PRELIMINARY Package Name Package Type Z44 44-Lead TSOP II Z44 44-Lead TSOP II ...

Page 9

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY62126V ...

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