CY7C1356BV25-166AC Cypress Semiconductor Corporation., CY7C1356BV25-166AC Datasheet
CY7C1356BV25-166AC
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CY7C1356BV25-166AC Summary of contents
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... Write operations are controlled by the Byte Write Selects (BW –BW a CY7C1356BV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence ...
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... Logic Block Diagram-CY7C1356BV25 (512K x 18) ADDRESS A0, A1, A REGISTER 0 MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 CE2 CE3 ZZ Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. ...
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... DQb DQa 18 63 DQa DQb DDQ 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1354BV25 CY7C1356BV25 DDQ DQPa 74 DQa 73 DQa DQa 69 DQa (512K × 18 DQa 63 DQa DQa 59 DQa DDQ Page DDQ DDQ ...
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... Document #: 38-05292 Rev. *E 119-ball BGA Pinout CY7C1354BV25 (256K × 36) – 14 × 22 BGA E(18 ADV/ DQP CLK CEN DQP MODE V DD E(72 TMS TDI TCK CY7C1356BV25 (512K x 18)– BGA E(18 ADV/ CLK CEN DQP MODE E(36) TMS TDI TCK CY7C1354BV25 CY7C1356BV25 DDQ A CE ...
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... DDQ DDQ DDQ N DQP DDQ P NC E(72 MODE E(36) A Document #: 38-05292 Rev. *E 165-Ball fBGA Pinout CY7C1354BV25 (256K × 36) – 13 × 15 fBGA CLK TDI TMS CY7C1356BV25 (512K × 18) – 13 × 15 fBGA CLK TDI TMS CY7C1354BV25 CY7C1356BV25 ADV/LD CEN WE OE E(18 DDQ DDQ V V ...
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... Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Clock input to the JTAG circuitry. Power supply inputs to the core of the device. CY7C1354BV25 CY7C1356BV25 controls DQ and DQP , ...
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... OE input signal. This allows the external logic to present the data on DQ and DQP (DQ a,b,c,d for CY7C1356BV25). In addition, the address for the subse- quent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). ...
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... Document #: 38-05292 Rev. *E the subsequent clock rise, the chip enables ( and WE inputs are ignored and the burst counter is incre- 3 mented. The correct BW (BW BW for CY7C1356BV25) inputs must be driven in each a,b /DQP cycle of the burst write in order to write the correct bytes of a,b a,b data. ...
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... Write Byte d – (DQ and DQP d d) Write Bytes d, a Write Bytes d, b Write Bytes Write Bytes d, c Write Bytes Write Bytes Write All Bytes Function (CY7C1356BV25) Read Write – No Bytes Written Write Byte a − (DQ and DQP a a) Write Byte b – (DQ and DQP b b) ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1354BV25/CY7C1356BV25 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance ...
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... When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR Document #: 38-05292 Rev. *E CY7C1354BV25 CY7C1356BV25 state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency MHz, while the SRAM clock operates more than an order of magnitude faster ...
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... TEST-LOGIC/ 0 IDLE Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05292 Rev. *E [9] 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE- EXIT2-DR 1 UPDATE- CY7C1354BV25 CY7C1356BV25 1 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- ...
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... I OL GND ≤ V ≤ DDQ GND ≤ V ≤ DDQ [12, 13] Over the Operating Range Description (AC) > −0.5V for t < t /2; undershoot: V /2. IL TCYC / ns CY7C1354BV25 CY7C1356BV25 0 Selection 0 Circuitry 0 0 Min. Max. 1.7 2.0 0.7 0.2 1 0.3 DD –0.3 0.7 –30 30 –30 30 Min. ...
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... Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-05292 Rev. *E Over the Operating Range (continued) Description DDQ TMSS t TMSH t TDIS t TDIH t TDOV CY7C1354BV25 CY7C1356BV25 [12, 13] Min. Max ALL INPUT PULSES 2.5V 1.25V 1 TCYC t TDOX Page Unit ...
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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05292 Rev. *E CY7C1354BV25 CY7C1356BV25 001 001 01011001000010110 Reserved for future use. 00000110100 00000110100 1 1 Bit Size Description CY7C1354BV25 CY7C1356BV25 Description Reserved for version number. Allows unique identification of SRAM vendor. Indicate the presence register. Page ...
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... Boundary Scan Exit Order (×36) Bit # 165-Ball B10 43 A10 44 C11 45 E10 46 F10 47 G10 48 D10 49 D11 50 E11 51 F11 G11 52 H11 53 J10 54 K10 55 L10 56 M10 57 J11 58 K11 59 L11 60 M11 61 N11 62 R11 63 R10 64 P10 CY7C1354BV25 CY7C1356BV25 (continued) 119-Ball ID 165-Ball Not Bonded Not Bonded (Preset to 1) (Preset ...
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... Not Bonded 60 (Preset to 0) Not Bonded 61 (Preset R11 63 R10 64 P10 CY7C1354BV25 CY7C1356BV25 (continued) 119-Ball ID 165-Ball Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded (Preset to 0) (Preset to 0) ...
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... BGA Max 25° MHz 2. 2.5V DD DDQ /2), undershoot: V (AC)> -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < CY7C1354BV25 CY7C1356BV25 Ambient Temperature 0°C to +70°C 2. –40°C to +85°C Min. Max. 2.375 2.625 2.375 V DD 2.0 0.4 1 ...
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... V power is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ = 2.5V. CY7C1354BV25 CY7C1356BV25 ALL INPUT PULSES V DD 90% 1.25V 10% 0V < 1.0 ns (c) fBGA Typ. TQFP Typ. ...
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... D(A2) D(A2+1) BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH,CE is HIGH CY7C1354BV25 CY7C1356BV25 -200 -166 Min. Max. Min. Max. 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ...
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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle Document #: 38-05292 Rev. *E [23,24,26 D(A1) Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE CY7C1354BV25 CY7C1356BV25 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED Page ...
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... Note: 27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05292 Rev RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1354BV25 CY7C1356BV25 t ZZREC Page ...
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... CY7C1356BV25-200AC CY7C1354BV25-200AI CY7C1356BV25-200AI CY7C1354BV25-200BGC CY7C1356BV25-200BGC CY7C1354BV25-200BGI CY7C1356BV25-200BGI CY7C1354BV25-200BZC CY7C1356BV25-200BZC CY7C1354BV25-200BZI CY7C1356BV25-200BZI 166 CY7C1354BV25-166AC CY7C1356BV25-166AC CY7C1354BV25-166AI CY7C1356BV25-166AI CY7C1354BV25-166BGC CY7C1356BV25-166BGC CY7C1354BV25-166BGI CY7C1356BV25-166BGI CY7C1354BV25-166BZC CY7C1356BV25-166BZC 166 CY7C1354BV25-166BZI CY7C1356BV25-166BZI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05292 Rev. *E CY7C1354BV25 CY7C1356BV25 51-85050-*A Page ...
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... Package Diagrams (continued) Document #: 38-05292 Rev. *E 119-Lead BGA ( 2.4mm) BG119 CY7C1354BV25 CY7C1356BV25 51-85115-*B Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1354BV25 CY7C1356BV25 51-85122-*C Page ...
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... Document History Page Document Title: CY7C1354BV25/CY7C1356BV25 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05292 REV. ECN No. Issue Date ** 114767 08/08/02 *A 117938 08/20/02 *B 126206 04/11/03 *C 206704 See ECN *D 239272 See ECN *E 280209 See ECN Document #: 38-05292 Rev. *E Orig. of ...