CY7C1357B-100AC Cypress Semiconductor Corporation., CY7C1357B-100AC Datasheet
CY7C1357B-100AC
Related parts for CY7C1357B-100AC
CY7C1357B-100AC Summary of contents
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... JTAG boundary scan for BGA and fBGA packages • Burst Capability—linear or interleaved burst order • Low standby power Functional Description The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without ...
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... REGISTER MODE CE CLK C CEN ADV/ ADDRESS BW B A0, A1, A REGISTER BW C MODE CLK C CEN OE CE1 CE2 CE3 ZZ ADV/ Logic Block Diagram – CY7C1357B (512K x 18) WE ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN OE CE1 CE2 CE3 ZZ ADV/ CE1 CE2 CE3 ZZ Document #: 38-05117 Rev A1 A0 ...
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... Pin Configurations DQP DDQ BYTE DDQ Vss/DNU DDQ BYTE DDQ DQP 30 D Document #: 38-05117 Rev. *B 100-lead TQFP CY7C1355B CY7C1355B CY7C1357B 80 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A Page ...
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... Pin Configurations (continued DDQ DDQ Vss/DNU BYTE DDQ DQP DDQ Document #: 38-05117 Rev. *B 100-lead TQFP CY7C1357B CY7C1355B CY7C1357B DDQ DQP DDQ BYTE DDQ DDQ Page ...
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... Document #: 38-05117 Rev. *B 119-ball BGA (3 Chip Enables with JTAG) CY7C1355B (256K x 36 18M CE A ADV/ DQP CLK CEN DQP MODE 72M A A TMS TDI TCK CY7C1357B (512K x 18 18M CE A ADV/ CLK CEN DQP MODE 36M TMS TDI TCK CY7C1355B CY7C1357B DDQ A CE ...
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... V B DDQ DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05117 Rev. *B 165-ball fBGA (3 Chip enable with JTAG) CY7C1355B (256K x 36 CLK TDI A0 A TMS CY7C1357B (512K x 18 CLK TDI TMS CY7C1355B CY7C1357B CEN ADV/ 18M DDQ DDQ DDQ V V ...
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... ZZ “Sleep” Input. This active HIGH input places the de- Asynchronous vice in a non-time critical “sleep” condition with data integ- rity preserved. During normal operation, this pin can be connected to V CY7C1355B CY7C1357B Description are fed to the two-bit burst counter. [1:0] , and CE 2 ...
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... Serial data-In to the JTAG circuit. Sampled on the rising input edge of TCK. If the JTAG feature is not being utilized, this Synchronous pin can be left floating or connected resistor. This pin is not available on TQFP packages. CY7C1355B CY7C1357B Description are placed in a three-state condition. The [A:D] . During Write sequences controlled by BW correspondingly ...
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... CY7C1355B–Pin Definitions Name TQFP BGA TMS - U2 TCK - U4 NC 16,38,39,42, B1,C1,R1, 43,66,84 T1,T2,J3, A4,D4,L4, J5,R5,T6, U6,B7,C7 /DNU CY7C1357B–Pin Definitions Name TQFP BGA 37,36,32,33, P4,N4,A2 34,35,44,45, C2,R2,T2, 46,47,48,49, A3,B3,C3, 50,80,81,82, T3,A5,B5, 83,99,100 C5,T5,A6, C6,R6,T6 93,94 G3, ADV/LD CLK Document #: 38-05117 Rev. *B (continued) ...
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... CY7C1357B–Pin Definitions Name TQFP BGA CEN 58,59,62,63, P7,K7,G7 68,69,72,73, E7,F6,H6, 8,9,12,13, L6,N6,D1, 18,19,22,23 H1,L1,N1, E2,G2,K2, M2 74,24 D6,P2 DQP [A:B] MODE 15,41,65,91 C4,J2,J4, DD J6,R4 V 4,11,20,27, A1,A7,F1, DDQ 54,61,70,77 F7,J1,J7, M1,M7,U1 ,U7 Document #: 38-05117 Rev. *B (continued) fBGA I/O B8 Input- Output Enable, asynchronous input, active LOW. ...
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... CY7C1357B–Pin Definitions Name TQFP BGA V 5,10,17,21, D3,D5,E3, SS 26,40,55,60, E5,F3,F5, 67,71,76,90 G5,H3, H5,K3,K5, L3,M3, M5,N3, N5,P3,P5 TDO - U5 TDI - U3 TMS - U2 TCK - U4 NC 1,2,3,6,7,16, A4,B1,B7, 25,28,29,30, C1,C7,D2, 38,39,42,43, D4,D7,E1, 51,52,53,56, E6,H2,F2, 57,66,75,78, G1,G6, 79,84,95,96 H7,J3,J5, K1,K6,L4, L2,L7,M6, N2,N7,L7, P1,P6,R1, R5,R7,T1, T4,U6 V /DNU Document #: 38-05117 Rev. *B ...
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... Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1355B/CY7C1357B is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP Doing so will three-state the output drivers ...
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... The device must be deselected prior to entering the “sleep” mode. CE the duration of t Test Conditions ZZ > V – 0. > V – 0. < 0.2V This parameter is sampled This parameter is sampled CY7C1355B CY7C1357B Second Third Fourth Address Address Address A1: A0 A1 ...
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... data when OE is active valid. Appropriate write will be done based on which byte write is active. [A:D] CY7C1355B CY7C1357B CEN CLK L->H Three-State L->H Three-State L->H Three-State L->H Three-State L->H Data Out ( L->H Data Out ( L->H Three-State L->H Three-State L->H Data In ( L->H Data In (D) ...
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... Write Byte C – (DQ and DQP ) C C Write Byte D – (DQ and DQP ) D D Write All Bytes [2, 3] Truth Table for Read/Write Function (CY7C1357B) Read Write - No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write All Bytes Document #: 38-05117 Rev ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1355B/CY7C1357B incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TAP controller’s capture set-up plus hold time (t The SRAM clock input might not be captured correctly if there PRELOAD portion way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1355B CY7C1357B instructions. Unlike the SAMPLE/PRELOAD plus ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE [10, 11] Over the operating Range Description / ns CY7C1355B CY7C1357B TDOV t TDOX UNDEFINED Min. Max Page Unit ns ...
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... DDQ DDQ I = 100 µ DDQ V DDQ V DDQ V DDQ V DDQ V DDQ GND < V < DDQ CY7C1355B CY7C1357B 1.25V 50 TDO 20pF O Min. Max. = 3.3V 2.4 = 2.5V 2.0 = 3.3V 2.9 = 2.5V 2.1 = 3.3V 0.4 = 2.5V 0.4 = 3.3V 0.2 = 2.5V 0.2 = 3. 2.5V 1 ...
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... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1355B CY7C1357B Description Describes the version number Reserved for Internal Use Defines memory type and architecture ...
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... Internal Internal Internal Internal Internal Internal C D2 DQP 24 Internal Internal Internal Internal CY7C1355B CY7C1357B CY7C1357B (512K x 18) Signal BIT# BALL ID Name CLK CEN ADV/ Internal Internal Internal Internal Internal 46 P2 Internal 47 N1 Internal DQP Internal Internal Internal Internal A Internal 59 Internal Internal ...
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... Internal C C1 DQP 24 Internal Internal Internal Internal CY7C1355B CY7C1357B CY7C1357B (512K x 18) BALL Signal BIT# BALL ID ID Name B6 CLK CEN ADV/ Internal B10 A 43 Internal A10 A 44 Internal A11 A 45 Internal Internal 46 N1 Internal 47 M1 Internal 48 L1 C11 DQP D11 DQ 50 ...
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... DD IN 0.3V 0, inputs static /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1355B CY7C1357B Ambient Temperature V DD 0°C to +70°C 3.3V– 5%/+10% 2.5V – 5% -40°C to +85°C Min. Max. 3.135 3.6 3.135 ...
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... EIA / JESD51. Test Conditions T = 25qC MHz 3.3V 2.5V DDQ R = 317: 3.3V OUTPUT 351: INCLUDING JIG AND (b) SCOPE R = 1667: 2.5V OUTPUT =1538: INCLUDING JIG AND (b) SCOPE CY7C1355B CY7C1357B TQFP BGA fBGA Package Package Package TQFP BGA fBGA Package Package Package ALL INPUT PULSES V ...
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... DDQ is the time that the power needs to be supplied above V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1355B CY7C1357B 117 MHz 100 MHz Min. Max. Min. Max 8 ...
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... A4 t CDV t DOH t CLZ D(A2) D(A2+1) Q(A3) t OEHZ BURST READ READ WRITE Q(A3) Q(A4) D(A2+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1355B CY7C1357B OEV t CHZ Q(A4+1) Q(A4) D(A5) Q(A6) t DOH t OELZ BURST WRITE READ WRITE READ D(A5) Q(A6) ...
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... CDV t DOH t CLZ D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED CY7C1355B CY7C1357B OEV t CHZ Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE D(A5) Q(A6) D(A7) 10 D(A7) DESELECT Page ...
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... CY7C1357B-133AC CY7C1355B-133AI CY7C1357B-133AI CY7C1355B-133BGC CY7C1357B-133BGC CY7C1355B-133BGI CY7C1357B-133BGI CY7C1355B-133BZC CY7C1357B-133BZC CY7C1355B-133BZI CY7C1357B-133BZI 117 CY7C1355B-117AC CY7C1357B-117AC CY7C1355B-117AI CY7C1357B-117AI CY7C1355B-117BGC CY7C1357B-117BGC CY7C1355B-117BGI CY7C1357B-117BGI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05117 Rev ZZI I DDZZ High-Z DON’ ...
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... Ordering Information (continued) Speed (MHz) Ordering Code CY7C1355B-117BZC CY7C1357B-117BZC CY7C1355B-117BZI CY7C1357B-117BZI 100 CY7C1355B-100AC CY7C1357B-100AC CY7C1355B-100AI CY7C1357B-100AI CY7C1355B-100BGC CY7C1357B-100BGC CY7C1355B-100BG ICY7C1357B-100BGI CY7C1355B-100BZC CY7C1357B-100BGC CY7C1355B-100BZI CY7C1357B-100BGI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05117 Rev. *B ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05117 Rev. *B CY7C1355B CY7C1357B 51-85050-*A Page ...
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... Package Diagrams (continued) Document #: 38-05117 Rev. *B 119-Lead PBGA ( 2.4 mm) BG119 CY7C1355B CY7C1357B 51-85115-*B Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1355B CY7C1357B 51-85122-*C Page ...
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... Document History Page Document Title: CY7C1355B/CY7C1357B 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05117 REV. ECN NO. Issue Date ** 117908 08/28/02 *A 123161 12/18/02 *B 205060 See ECN Document #: 38-05117 Rev. *B Orig. of Change RCS New Data Sheet RCS Removed Preliminary Statue (all pages). ...