CY7C374-83AC Cypress Semiconductor Corporation., CY7C374-83AC Datasheet
CY7C374-83AC
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CY7C374-83AC Summary of contents
Page 1
... The CY7C374 is a register intensive 128-Macrocell CPLD. Ev- ery two macrocells in the device feature an associated I/O pin, resulting in 64 I/O pins on the CY7C374. In addition, there are two dedicated inputs and four input/clock pins. CLOCK INPUTS ...
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... GND 9 I/O I 7C374– TQFP Top View 100 CY7C374 PGA Bottom View I/O I/O I/O I/O V I/O I I/O I/O I/O I I/O I/O I I/O V GND 29 CC GND CLK2 / ...
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... PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C374 to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM ...
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... Tested initially and after any design or process changes that may affect these parameters. 6. Measured with 16-bit counter programmed into each logic block for the CLCC and CPGA packages max. I for max I/O 5 CY7C374 Ambient Temperature + + +125 C 5V 10% Min. ...
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... INCLUDING JIG AND SCOPE (b) 7C374–5 2.08V (COM'L) 2.13V (MIL) Output Waveform Measurement Level V OH 0. 0.5V is measured with 35-pF AC Test Load. EA CY7C374 ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND 2 ns 7C374– Page ...
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... WH Document #: 38-03021 Rev. ** [10] Description [5] [ 1 SCS CY7C374 7C374-66 7C374-100 7C374-83 7C374L-66 Min. Max. Min. Max. Min. Max ...
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... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 11. This specification is intended to guarantee interface compatibility of the other members of the CY7C370 family with the CY7C374. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...
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... OUTPUT Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Registered Output INPUT CLOCK REGISTERED OUTPUT CLOCK Document #: 38-03021 Rev ICO CY7C374 7C374–7 7C374–8 7C374–9 Page ...
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... LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK UTPUT REGISTER CLOCK Document #: 38-03021 Rev PDL t ICOL t ICS t ICS CY7C374 t CO 7C374–10 t PDLL SCS 7C374–12 Page ...
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... LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Document #: 38-03021 Rev PDL CY7C374 t ICO Page 7C374–13 7C374–14 7C374–15 ...
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... Switching Waveforms (continued) Output Enable/Disable INPUT OUTPUTS Ordering Information Speed Package (MHz) Ordering Code 100 CY7C374-100AC CY7C374-100GC CY7C374-100JC 83 CY7C374-83AC CY7C374-83GC CY7C374-83JC CY7C374-83AI CY7C374-83JI CY7C374-83GMB CY7C374-83YMB 66 CY7C374-66AC CY7C374-66GC CY7C374-66JC CY7C374-66AI CY7C374-66JI CY7C374-66GMB CY7C374-66YMB CY7C374L-66AC CY7C374L-66JC Document #: 38-03021 Rev Name Package Type ...
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... 10, 11 PDL t 9, 10, 11 PDLL 10, 11 ICO t 9, 10, 11 ICOL 10, 11 ICS CY7C374 Page ...
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... Package Diagrams 100-Pin Thin Quad Flat Pack A100 Document #: 38-03021 Rev. ** CY7C374 Page ...
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... Package Diagrams (continued) 84-Lead Plastic Leaded Chip Carrier J83 Document #: 38-03021 Rev. ** 84-Pin Grid Array (Cavity Up) G84 CY7C374 51-80015-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C374 Page ...
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... Document Title: CY7C374 UltraLogic™ 128-Macrocell Flash CPLD Document Number: 38-03021 REV. ECN NO. Issue Date ** 106324 05/08/01 Document #: 38-03021 Rev. ** Orig. of Change SZV Transferred from Spec number: 38-00214 to 38-03021. CY7C374 Description of Change Page ...