CY7C4831-15AC Cypress Semiconductor Corporation., CY7C4831-15AC Datasheet
CY7C4831-15AC
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CY7C4831-15AC Summary of contents
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... Double high speed, low power, first-in first-out (FIFO) memories • Double 256 x 9 (CY7C4801) • Double 512 x 9 (CY7C4811) • Double (CY7C4821) • Double (CY7C4831) • Double (CY7C4841) • Double (CY7C4851) • Functionally equivalent to two CY7C4201/4211/4221/ 4231/4241/4251 FIFOs in a single package • ...
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... CY7C4841 39 10 CY7C4851 RSA CY7C4801/4811/4821 CY7C4831/4841/4851 LDA LDB EFA PAEA PAFA FFA EFB PAEB PAFB FFB READ POINTER B READ CONTROL B RCLKB RENB1 48X1–1 RENB2 QB 0 FFB EFB OEB RENB2 RCLKB RENB1 ...
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... C to +150 C Operating Range +125 C Range 0.5V to +7.0V Commercial [2] Industrial 0.5V to +7.0V 0.5V to +7.0V Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up the “instant on” case temperature. A CY7C4801/4811/4821 CY7C4831/4841/4851 7C48X1-25 7C48X1- CY7C4841 ...
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... Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When (OEA,OEB) is LOW, the FIFO’s data outputs drive the bus to which they are connected. If (OEA,OEB) is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. CY7C4801/4811/4821 CY7C4831/4841/4851 Page [+] Feedback ...
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... Max GND , 10 + < V < Com’l 60 Ind 70 Test Conditions MHz 5.0V CC [7, 8] 3.0V R2 GND 680 3 ns 48X1–4 1.91V CY7C4801/4811/4821 CY7C4831/4841/4851 7C48X1-25 7C48X1-35 Max. Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 0 2 0.8 0.5 0.8 0.5 0.8 V +10 10 ...
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... CY7C4801/4811/4821 CY7C4831/4841/4851 7C48X1-25 7C48X1-35 Unit 40 28.6 MHz ...
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... CLKH CLKL NO OPERATION t REF t A VALID DATA t OE [12] t SKEW1 SKEW1 CY7C4801/4811/4821 CY7C4831/4841/4851 ENH NO OPERATION NO OPERATION t WFF 48X1–6 t REF t OHZ 48X1–7 , then (FFA,FFB) may not change state until the SKEW1 , then (EFA,EFB) may not change state until the next ...
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... Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make the pin act as a load enable for the programmable flag offset registers. Document #: 38-06005 Rev RSR RSS t t RSR RSS t t RSR RSS t RSF t RSF t RSF CY7C4801/4811/4821 CY7C4831/4841/4851 [14] OEA(OEB)=1 48X1–8 OEA(OEB)=0 Page [+] Feedback ...
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... The first word is available the cycle after (EFA, EFB) goes HIGH, always. Document #: 38-06005 Rev FRL t REF OLZ When t < minimum specification, t CLK SKEW1 SKEW1 CY7C4801/4811/4821 CY7C4831/4841/4851 48X1–9 (maximum) = either 2 FRL CLK SKEW1 CLK SKEW1 Page [+] Feedback ...
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... WENA2(WENB2) [16] (if applicable) t FRL RCLKA(RCLKB) t SKEW1 EFA(EFB) RENA1, RENA2 (RENB1,RENB2) LOW OEA(OEB) DATA IN OUTPUT REGISTER ( Document #: 38-06005 Rev. *A CY7C4801/4811/4821 CY7C4831/4841/4851 t DS DATA WRITE2 t ENS t ENS REF REF SKEW1 ENH t ENH [16] t FRL t REF DATA READ 48X1– ...
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... LOW OEA(OEB DATA IN OUTPUT REGISTER Document #: 38-06005 Rev WRITE [11 SKEW1 DATA WRITE t WFF t ENS DATA READ CY7C4801/4811/4821 CY7C4831/4841/4851 NO WRITE DATA WRITE t WFF t ENH t A NEXT DATA READ 48X1–11 Page [+] Feedback ...
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... If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when (PAFA,PAFB) goes LOW. 22. (PAFA,PAFB) offset = m. 23. 256-m words in FIFO for CY7C4801, 512-m words for CY7C4811, 1024-m words for CY7C4821, 2048-m words for CY7C4831, 4096-m words for CY7C4841, 8192-m words for CY7C4851. ...
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... Document #: 38-06005 Rev CLKL t ENH t DH PAE OFFSET PAF OFFSET LSB MSB t CLKL t ENH t A UNKNOWN PAE OFFSET LSB CY7C4801/4811/4821 CY7C4831/4841/4851 PAF OFFSET LSB MSB 48X1–14 PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB 48X1–15 Page [+] Feedback ...
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... WENB2/LDB) is LOW and both (RENA1,RENB1) and (RENA2,RENB2) are LOW. LOW-to-HIGH transitions of (RCLKA,RCLKB) read register contents to the data out- puts. Writes and reads should not be preformed simultaneously on the offset registers. CY7C4801/4811/4821 CY7C4831/4841/4851 (WENA2/LDA, WENB2/LDB) and and Page ...
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... LOW when the number of unread words in the FIFO is greater than or equal to CY7C4801 (256–m), CY7C4811 (512–m), CY7C4821 (1K–m), CY7C4831 (2K–m), CY7C4841 (4K–m), and CY7C4851 (8K–m). (PAFA,PAFB) is set HIGH by the LOW-to-HIGH transition of (WCLKA,WCLKB) when the number of available memory locations is greater than m ...
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... Full Flag. CY7C4811 CY7C4821 0 [26 (n+1) to (1024 (m+1)) [27] [27] to 511 (1024 m) to 1023 1024 CY7C4851 [26 [27] (8192 m) to 8191 H 8192 L CY7C4801/4811/4821 CY7C4831/4841/4851 FF PAF PAE PAF PAE EF H ...
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... RESET (RSA,RSB) ( DATA OUT READ CLOCK (RCLKA,RCLKB) CY7C4801 READ ENABLE 1 (RENA1,RENB1) CY7C4811 CY7C4821 CY7C4831 OUTPUT ENABLE (OEA,OEB) CY7C4841 CY7C4851 PROGRAMMABLE(PAEA,PAEA) EMPTY FLAG(EFA,EFB) Read Enable 2 (RENA2,RENB2) Used in a Single Device Configuration. CY7C4801/4811/4821 CY7C4831/4841/4851 QA ( 48X1–16 Page [+] Feedback ...
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... OEA 2048 x 9 2048 x 9 WENB2/LDB 4096 x 9 4096 x 9 8192 x 9 8192 (RENA2) Read Enable 2 (RENB2) width-expansion. CY7C4801/4811/4821 CY7C4831/4841/4851 the Write Enable 2/Load RESET READCLOCK RCLKB READ ENABLE RENB1 OUTPUT ENABLE OEB EFA EMPTY FLAG EFB Q ...
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... Depth Expansion configuration when the following conditions are met: 1. WENA2/LDA and WENB2/LDB pins are held HIGH during Reset so that these pins operate as second Write Enables. 2. External logic is used to control the flow of data. CY7C4801/4811/4821 CY7C4831/4841/4851 PROCESSOR A CLOCK ADDRESS CONTROL DATA ...
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... Thin Quad Flatpack Industrial 64-Lead Thin Quad Flatpack Commercial 64-Lead Thin Quad Flatpack Industrial 64-Lead Thin Quad Flatpack Commercial 64-Lead Thin Quad Flatpack Industrial 64-Lead Thin Quad Flatpack Commercial 64-Lead Thin Quad Flatpack Industrial CY7C4801/4811/4821 CY7C4831/4841/4851 Range Range Range Page [+] Feedback ...
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... Ordering Information (continued) Double 2Kx9 FIFO Speed Package (ns) Ordering Code Name 10 CY7C4831-10AC A65 CY7C4831-10AI A65 15 CY7C4831-15AC A65 CY7C4831-15AI A65 25 CY7C4831-25AC A65 CY7C4831-25AI A65 35 CY7C4831-35AC A65 CY7C4831-35AI A65 Double 4Kx9 FIFO Speed Package (ns) Ordering Code Name 10 CY7C4841-10AC A65 CY7C4841-10AI A65 15 CY7C4841-15AC A65 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 64-Lead Thin Plastic Quad Flat Pack A65 CY7C4801/4811/4821 CY7C4831/4841/4851 Page [+] Feedback ...
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... Document Title: CY7C4801/4811/4821/CY7C4831.4841/4851 256/512/1K/2K/4K/ Double Sync (TM) Fifos Document Number: 38-06005 Issue Orig. of REV. ECN NO. Date Change ** 106466 07/11/01 *A 122258 12/26/02 Document #: 38-06005 Rev. *A Description of Change SZV Change from Spec Number: 38-00538 to 38-06005 RBI Power up requirements added to Operating Conditions Information CY7C4801/4811/4821 CY7C4831/4841/4851 Page ...