IDT74LVC573APG Integrated Device Technology, Inc., IDT74LVC573APG Datasheet

IDT74LVC573APG

Manufacturer Part Number

IDT74LVC573APG

Description

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT74LVC573APG.pdf (6 pages)

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

IDT74LVC573APG

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IDT

Quantity:

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

IDT74LVC573APG

Manufacturer:

IDT

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5 608

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FEATURES:

• 0.5 MICRON CMOS Technology

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

• V

• CMOS power levels (0.4 W typ. static)

• Rail-to-rail output swing for increased noise margin

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

• Available in SOIC, SSOP, QSOP, and TSSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

FUNCTIONAL BLOCK DIAGRAM

IDT74LVC573A

3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH

machine model (C = 200pF, R = 0)

= 3.3V ± 0.3V, Normal Range

= 2.7V to 3.6V, Extended Range

3.3V CMOS OCTAL

TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

AND 5 VOLT TOLERANT I/O

TO SEVEN OTHER CHANNELS

DESCRIPTION:

metal CMOS technology. The device features 3-state outputs designed

specifically for driving highly capacitive or relatively low-impedance loads,

and is particularly suitable for implementing buffer registers, input-output (I/

O) ports, bidirectional bus drivers, and working registers.

(D) inputs. When LE is taken low, the Q outputs are latched at the logic levels

at the D inputs.

outputs in either a normal logic state (high or low logic levels) or a high-

impedance state. In the high-impedance state, the outputs neither load nor

drive the bus lines significantly. The high-impedance state and increased

drive provide the capability to drive bus lines without interface or pullup

components. OE does not affect the internal operations of the latch. Old data

can be retained or new data can be entered while the outputs are in the

high-impedance state.

driver is capable of driving a moderate to heavy load while maintaining

speed performance.

the use of this device as a translator in a mixed 3.3V/5V system environ-

ment.

The LVC573A octal transparent D-type latch is built using advanced dual

While the latch-enable (LE) input is high, the Q outputs follow the data

A buffered output-enable (OE) input can be used to place the eight

The LVC573A has been designed with a ±24mA output driver. This

Inputs can be driven from either 3.3V or 5V devices. This feature allows

INDUSTRIAL TEMPERATURE RANGE

IDT74LVC573A

MARCH 1999

DSC-4627/1

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IDT74LVC573APG Summary of contents

Page 1

... FUNCTIONAL BLOCK DIAGRAM The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE © 1999 Integrated Device Technology, Inc. 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: The LVC573A octal transparent D-type latch is built using advanced dual metal CMOS technology ...

Page 2

IDT74LVC573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH PIN CONFIGURATION GND 10 SOIC/ SSOP/ QSOP/ ...

Page 3

IDT74LVC573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW Voltage Level ...

Page 4

IDT74LVC573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH OPERATING CHARACTERISTICS, V Symbol Parameter C Power Dissipation Capacitance per Latch Outputs enabled PD C Power Dissipation Capacitance per Latch Outputs disabled PD SWITCHING CHARACTERISTICS Symbol Parameter t Propagation Delay PLH t xD ...

Page 5

IDT74LVC573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 300 LZ ...

Page 6

IDT74LVC573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH ORDERING INFORMATION XX IDT LVC X XXXX Temp. Range Bus-Hold Device Type CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 XX Package SO Small Outline IC (gull wing) PY Shrink Small Outline ...

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