ISL3873IK Intersil Corporation, ISL3873IK Datasheet
ISL3873IK
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ISL3873IK Summary of contents
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... NUMBER RANGE ( C) PACKAGE ISL3873IK - 192 BGA ISL3873IK96 - Tape and Reel 1000 Units /Reel 1 February 2001 New Features of the ISL3873 • USB Host Interface Supports USB V1.1 at 12Mbps. • New Start Up Modes Allow the PCMCIA Card Information Structure to be Initialized From a Serial EEPROM. This ...
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Simplified Block Diagram HOST COMPUTER DATA ADDRESS CONTROL PC CARD HOST INTERFACE MICRO- PROGRAMMED MAC ENGINE WEP ENGINE ON-CHIP ROM MEMORY CONTROLLER ON-CHIP RAM MEDIUM ACCESS ADDRESS DATA SELECT EXTERNAL SRAM AND FLASH MEMORY 2 ISL3873 USB ISL3873 USB HOST ...
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ISL3873 Signal Descriptions PIN NAME PIN I/O TYPE HA0-9 5V tol, CMOS, Input, 50K Pull Down HCE1- 5V tol, CMOS, Input, 50K Pull Up HCE2- 5V tol, CMOS, Input, 50K Pull Up HD0-15 5V tol, BiDir, 2mA, 50K Pull Down ...
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MAC RADIO INTERFACE AND GENERAL PURPOSE PORT PINS PIN NAME PIN I/O TYPE PJ4 CMOS BiDir, 2mA PJ5 CMOS BiDir, 2mA, 50K Pull Up PJ6 CMOS BiDir, 2mA PJ7 CMOS BiDir, 2mA, 50K Pull Up PK0 CMOS BiDir, 2mA, ST, ...
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PIN NAME PIN I/O TYPE ANTSEL O ANTSEL O TestMode I/O CompCap1 I CompCap2 I CompRes1 I CompRes2 I DBG(0-4) I/O PIN NAME PIN I/O TYPE V Power DDA V Power DD SUPPLY5V Power V Ground SSA V Ground sub ...
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PIN NUMBER SIGNAL NAME PIN NUMBER MA9 B4 MA12 MA18 B7 DBG1 B8 HD12 B9 HCE1 B10 V DD B11 HIORD B12 HA8 B13 HWE B14 HA4 B15 NC B16 DBG4 C1 MA6 ...
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Absolute Maximum Ratings Supply Voltage 3.6V ...
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AC Electrical Specifications (Continued) PARAMETER SYNTHCLK(PK1) Width Hi SYNTHCLK(PK1) Width Lo SERIAL PORT SYNTHCLK(PK1) Clock Period Low Width Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD, SYNTHDATA(PK2) Outputs Setup Time of SYTHNDATA(PK2) Read to SYTHNCLK(PK1) Falling Edge Hold Time ...
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Waveforms ADDRESS MA(17..1) RAMCS_ MOE_ t S2 MD(15..0) ADDRESS MA(17..1) RAMCS_ MWE_ MD(15..0) SYNTHCLK SYNLE SPCSPWR t D1 SYNTHDATA 9 ISL3873 FIGURE 1. EXTERNAL MEMORY READ TIMING ...
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Waveforms (Continued) HA[15:0] HREG- HCE( HIORD- t SUA HINPACK- HWAIT- HD[15:0] HA[15:0] HREGN- HCE ( HIOWR- HWAIT- t SUIOWR HD[15:0] 10 ISL3873 t SUREG t HREG I t SUCE HCE t WIORD t DIORD t DFINPACK ...
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I ISL3873 MAC System Overview ISL3873 MD0..15 MA1..17 NVCS_ MOE_ MWEL_ MA0/MWEH_ RAMCS_ FIGURE 6. 8-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873 ISL3873 MA1..17 MD0..15 NVCS- MA0/MWEH- MLBE- RAMCS- MOE- MWEL- FIGURE 7. 16-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873 11 ISL3873 ...
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LARGE SERIAL EEPROM MISO (PJ2) SD (PJ1) ISL3873 SCLK (PJ0) CS# (TCLKIN) PULLUP External Memory Interface The ISL3873 provides separate external chip selects for code space and data storage space. Code space is accessible as data space through an overlay ...
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For 8-bit spaces, the ISL3873 dynamically configures pin MUBE-/MA0/MWEH- cycle-by-cycle as the address LSB. MWEL-/MWE- is the only write control, and MOE- is the read output enable. For 16-bit spaces constructed from 8-bit memories, the ISL3873 dynamically configures pin MUBE-/MA0/MWEH- ...
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Read to Attribute Space and Memory Mapped Registers • WAIT will assert until the memory arbitration and access have completed. Buffer Access Paths, BAP0 and BAP1 • An internal Pre-Read cycle to memory is initiated by a host Buffer Read ...
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FID ALLOCATE/ DEALLOCATE REQUEST OFFSET CENTER HOST BUS DATA PORT PRE-READ/ POST-WRITE FIGURE 9. BLOCK DIAGRAM OF A BUFFER ACCESS PATH USB Port The USB interface implemented in the ISL3873 complies with the Universal Serial Bus Specification Revision 1.1. dated ...
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PE1 PE2 TR_SW TR_SW_BAR PA_PE TABLE 2. POWER ENABLE STATES PE1 Power Down State 0 Receive State 1 Transmit State 1 PLL Active State 0 PLL Disable State X PLL_PE is controlled via the serial interface, and can be used ...
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CLKIN frequency. The MCLK prescaler generates glitch free output when the divisor is changed. This allows firmware to change the MCLK frequency during operation, which is especially useful to selectively reduce operating speed, thereby conserving power, ...
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Baseband Processor The Baseband Processor operation is controlled by the ISL3873 firmware. Detailed information on programming the Baseband Processor can be obtain by contacting the factory. BBP Packet Reception The receive demodulator scrutinizes I and Q for packet activity. When ...
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Pseudo Noise (PN) synchronization while the header includes the necessary data fields of the communications protocol to establish the physical layer link. The transmitter generates the synchronization preamble and header and knows when to make the DBPSK to ...
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DSSS BPSK 1Mbps BARKER DATA 1 BIT ENCODED TO ONE OF 2 CODE WORDS (TRUE-INVERSE) I OUT Q OUT 11 CHIPS CHIP 11 MC/S RATE SYMBOL 1 MS/S RATE I vs. Q PREAMBLE (SYNC) Start FRAME DELIMITER 128/56 BITS ...
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Defines the short preamble length minus the SFD in symbols. The 802.11 protocol requires a setting of 56d = 38h for the optional short preamble Defines the long preamble length minus the SFD in ...
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MSB), where c is the code word. The terms and 4 are defined below for 5.5Mbps and 11Mbps. This formula creates 8 complex chips (LSB to MSB) that are transmitted LSB first. The coding is ...
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Energy Detection measurement results), can assist the MAC in executing algorithms that can adapt to the environment. These algorithms can increase network throughput by minimizing collisions and reducing transmissions liable to errors. There are three measures ...
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RX_RF_AGC Pad Operation 30dB Pad Engaging (RF Chip Low Gain): If the AGC is not locked onto a packet, a '1' on the ifCompDet input will engage in the 30dB attenuation pad. This causes the AGC to go out of ...
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TX POWER RAMP 2 20 SYMBOLS AGC SETTLE AND LOCK AND INITIAL DETECTION V (ANALOG) DDA I REF V REF 6-BIT TX_AGC_IN ADC 6-BIT TX_IF_AGC DAC ANTSEL ANTSEL TX_PE FIGURE 17. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION Meanwhile signal quality and ...
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Channel Matched Filter (CMF) Description The receive section shown in Figure 19 operates on the RAKE receiver principle which maximizes the SNR of the signal by combining the energy of multipath signal components. The RAKE receiver is implemented with a ...
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SAMPLES AT 2X CHIP T0 CORRELATOR OUTPUT IS THE RESULT OF CORRELATING THE PSEUDO NOISE(PN) SEQUENCE WITH THE RECEIVED SIGNAL Data Demodulation in the CCK Modes In this mode, the demodulator uses Complementary Code Keying (CCK) modulation for the two ...
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V (ANALOG) DDA RX_IF_DET RX_IF_AGC AGC CONTROL 6-BIT RX_RF_AGC DAC DIVERSITY ANT SEL CONTROL 6-BIT RXI A/D 6 6-BIT RXQ A/D 6 COHERENT TIMING INTEGRATOR ANTENNA ANTSEL SWITCH ANTSEL CONTROL TIMING GENERATOR MCLK RESET RX_PE FIGURE 19. DSSS BASEBAND PROCESSOR, ...
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Demodulator Performance This section indicates the typical performance measures for a radio design. The performance data below should be used as a guide. In general, the actual performance depends on the application, interference environment, RF/IF implementation and radio component selection. ...
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RSSI Performance The RSSI value is reported on CR62 in hex and is linear with signal level in dB. Figure 22 shows the RSSI curve measured on a whole evaluation radio. This takes into account the full gain adjust range ...
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... Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/quality/iso.asp. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How- ever, no responsibility is assumed by Intersil or its subsidiaries for its use ...