ISL3874IK Intersil Corporation, ISL3874IK Datasheet
ISL3874IK
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ISL3874IK Summary of contents
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... TDMA or CSMA Packet Protocol Radios Ordering Information PART NUMBER RANGE ( ISL3874IK ISL3874IK96 PRISM® registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 ISL3874 File Number 8010 TEMP ...
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Simplified Block Diagram HOST COMPUTER DATA ADDRESS CONTROL PCI/CARD BUS 32 HOST INTERFACE MICRO- PROGRAMMED MAC ENGINE WEP ENGINE ON-CHIP ROM MEMORY CONTROLLER ON-CHIP RAM MEDIUM ACCESS CONTROLLER ADDRESS DATA SELECT EXTERNAL SRAM AND FLASH MEMORY 2 ISL3874 ISL3874 1 ...
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ISL3874 Signal Descriptions PIN PIN NAME NUMBER PIN I/O TYPE HAD31 A8 5V Tol, CMOS, BiDir PCI address/data bus bit 31. These signals make up the multiplexed PCI address and data bus on HAD30 A9 5V Tol, CMOS, BiDir PCI ...
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PIN PIN NAME NUMBER PIN I/O TYPE HBE0 H16 5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE0 applies to byte 0 (HAD7-HAD0). HINTA C6 CMOS, Output HRESET D6 5V Tol, CMOS, Input PCI reset. HFRAME B15 5V ...
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PIN NAME PIN NUMBER PL4-MA19 A4 CMOS BiDir, 2mA MA18 A3 CMOS BiDir, 2mA MA17 B4 CMOS BiDir, 2mA MA16 C3 CMOS TS Output, 2mA MA15 B3 CMOS TS Output, 2mA MA14 A1 CMOS TS Output, 2mA MA13 C2 CMOS ...
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PIN NAME PIN NUMBER MLBE L3 CMOS BiDir Output, 2mA, 50K Pull Up MOE L1 CMOS TS Output, 2mA, 50K Pull Up MWE/ MWEL L2 CMOS TS Output, 2mA, 50K Pull Up RAMCS K2 CMOS TS Output, 2mA, 50K Pull ...
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PIN NAME PIN NUMBER PJ0 P5 CMOS BiDir, 2mA, 50K Pull Up PJ1 T1 CMOS BiDir, 2mA, 50K Pull Down PJ2 R3 CMOS BiDir, 2mA, 50K Pull Down TCLKIN(CS) L4 I/O, 50K Pull Down PIN NAME PIN NUMBER XTALIN J2 ...
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PIN NAME PIN NUMBER PIN I/O TYPE GRESET L15 I TCLKIN(CS) L4 I/O, 50K Pull Down ANTSEL N15 O ANTSEL N16 O Test_Mode C4 I CompCap1 R15 I CompCap2 R13 I CompRes1 T15 I CompRes2 P13 I DBG4 B6 I/O ...
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Absolute Maximum Ratings Supply Voltage ...
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AC Electrical Specifications (Continued) PARAMETER SYNTHESIZER SYNTHCLK(PK1) Period SYNTHCLK(PK1) Width Hi SYNTHCLK(PK1) Width Lo SYNTHDATA(PK2) Hold Time from Falling Edge of SYNTHCLK(PK1) SYNTHCLK(PK1) Falling Edge to SYNLE Inactive SYSTEM INTERFACE - PCI TIMING Cycle Time, HPCLK Pulse Duration, HPCLK High ...
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Waveforms (Continued) ADDRESS MA(17..1) RAMCS MWE MD(15..0) SYNTHCLK SYNLE SPCSPWR t D1 SYNTHDATA 1.5V HPCLK PCI OUTPUT PCI INPUT 11 ISL3874 FIGURE 2. MAC EXTERNAL MEMORY WRITE TIMING CYC ...
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ISL3874 MD0..15 MA1..17 NVCS MOE MWEL MA0/MWEH RAMCS FIGURE 6. 8 BIT MEMORY INTERFACE ISL3874 MA1..17 MD0..15 NVCS MA0/MWEH MLBE RAMCS MOE MWEL FIGURE 7. 16-BIT MEMORY INTERFACE 12 ISL3874 SRAM 128Kx8 MD0..7 MA1.. SRAM 128Kx16 ADDR(0..16) ...
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LARGE SERIAL EEPROM MISO (PJ2) SD (PJ1) ISL3874 SCLK (PJ0) CS# (TCLKIN) PULLUP External Memory Interface The ISL3874 provides separate external chip selects for code space and data storage space. Code space is accessible as data space through an overlay ...
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MWEL/MWE is the only write control, and MOE is the read output enable. For 16-bit spaces constructed from 8-bit memories, the ISL3874 dynamically configures pin MA0/MWEH cycle-by- cycle as the high byte write enable, MWEL as the low write enable ...
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These are the minimum set of registers required for the card to respond to a target operation. The Memory Base Address register is used to set the starting address range this device will respond to. The maximum address space for ...
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PCI address lines on the PCI bus. HRESET - PCI Card reset signal. This reset signal only resets the PCI core. HFRAME - PCI Card FRAME cycle signal. FRAME is driven by ...
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Power Management queuing, and allows dynamic fragmentation and defragmentation by controller. Simple Allocate/Deallocate commands insure low host CPU overhead for memory management. Hardware buffer chaining provides high performance while reading and writing buffers. Data is transferred between the host ...
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PE1 and PE2 encoding details are found in Table 11. Note that during normal receive and transmit operation that PE1 is static and PE2 toggles for receive and transmit states. TABLE 11. POWER ENABLE STATES PE1 Power Down State 0 ...
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Table 12 summarizes the effect per pin. Table 13 provides the MD15 and MD14 bit values required to allow the ISL3874 to use the external Serial EEPROM bootup option. Baseband Processor The Baseband Processor operation is controlled by the ISL3874 ...
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TABLE 14 A/D SPECIFICATIONS PARAMETER MIN Full Scale Input Voltage (V ) 0.90 P-P Input Bandwidth (-0.5dB) - Input Capacitance (pF) - Input Impedance (DC (Sampling Frequency AGC Circuit The AGC circuit as shown ...
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For the 1 and 2Mbps modes, the transmitter accepts data from the external source, scrambles it, differentially encodes it as either DBPSK or DQPSK, and spreads it with the BPSK PN sequence. The baseband digital signals are then output to ...
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In the short preamble mode, the modem uses a synchronization field of 56 zero symbols along with an SFD transmitted at 1Mbps. The short header is transmitted at 2Mbps. The synchronization preamble is all 0’s to distinguish it from the ...
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Scrambling is done by division with a prescribed polynomial as shown in Figure 14. A shift register holds the last quotient and the output is the exclusive or of the data and the sum of taps in the shift register. ...
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DQPSK modulation as shown in the table. The symbols of the MPDU shall be numbered starting with “0” for the first symbol for the purposes of determining odd and even symbols. That is, the MPDU starts on an even numbered ...
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RSSI against a threshold. The threshold may be set to an absolute power value may be set above the measured noise floor. See CR35. The ISL3874 measures and stores the RSSI level ...
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ISL3874 from the HFA3783 chip. A '1' indicates its inputs are near saturation and it needs the RF chip to switch from high gain to low gain. RX_IF_Det is the input to the ...
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SQ1s will cause the part to finish the acquisition phase and enter the tracking phase. Prior to initial acquisition the NCO is inactive (0Hz) and carrier phase measurement are done on a symbol by symbol basis. After acquisition, coherent ...
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In the CCK mode, when a symbol decision error is made bits may be in error although on average only 3 bits will be in error. Secondly, when the bits are processed by the ...
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V (ANALOG) DD RX_IF_DET RX_IF_AGC AGC CONTROL 6-BIT RX-RF-AGC DAC DIVERSITY ANT SEL CONTROL 6-BIT RXI A/D 6 6-BIT RXQ A/D 6 COHERENT TIMING INTEGRATOR ANTSEL ANTENNA SWITCH ANTSEL CONTROL TIMING GENERATOR MCLK RESET RX_PE FIGURE 18. DSSS BASEBAND PROCESSOR, ...
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Data Demodulation in the CCK Modes In this mode, the demodulator uses Complementary Code Keying (CCK) modulation for the two highest data rates slaved to the low rate processor which it depends on for acquisition of initial timing ...
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CCK modes. The losses in both figures include RF and IF radio losses; they do not reflect the ISL3874 losses alone. The ISL3874 baseband processing losses from theoretical are, by themselves, a small percentage of the overall ...
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Signal Quality Estimate A signal quality measure is available on CR51 for use by the MAC. This measure is the SNR in the carrier tracking loop and can be used to determine when the demodulator is working near to the ...
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... Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How- ever, no responsibility is assumed by Intersil or its subsidiaries for its use ...