ISP1161A NXP Semiconductors, ISP1161A Datasheet
ISP1161A
Available stocks
Related parts for ISP1161A
ISP1161A Summary of contents
Page 1
... USB host only, a USB device only combination of a configurable USB host and USB device. ISP1161A brings high flexibility to the systems that have it built-in. For example, a system that uses an ISP1161A allows it not only to be connected USB hub with a USB downstream port, but also to be connected to a device that has a USB upstream port such as a USB printer, USB camera, USB keyboard or a USB mouse ...
Page 2
... Fig 1. ISP1161A operating as a USB device. DSC Fig 2. ISP1161A operating as a stand-alone USB host. PC (host) USB cable USB I/F Fig 3. ISP1161A operating as both USB host and device simultaneously. 9397 750 13962 Product data Full-speed USB single-chip host and device controller USB cable USB I/F EMBEDDED SYSTEM ...
Page 3
... Product data Full-speed USB single-chip host and device controller Complies with Universal Serial Bus Specification Rev. 2.0 The Host Controller portion of the ISP1161A supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s); the Device Controller portion of the ISP1161A supports data transfer at full-speed (12 Mbit/s) Combines the HC and the single chip On-chip DC complies with most USB device class specifi ...
Page 4
... Information Appliance (IA) Photo printer MP3 jukebox Game console. Description plastic low profile quad flat package; 64 leads; body 10 plastic low profile quad flat package; 64 leads; body 7 Rev. 03 — 23 December 2004 ISP1161A Version 10 1.4 mm SOT314-2 7 1.4 mm SOT414-1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 5
... H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17, 63 D15 ISP1161A HOST/ 28 DEVICE DACK2 27 AUTOMUX HOST BUS DACK1 34 INTERFACE EOT 26 DREQ2 25 DREQ1 30 INT2 DEVICE BUS 29 INTERFACE INT1 37 D_WAKEUP 36 D_SUSPEND 32 RESET POWER-ON RESET 3 VOLTAGE ...
Page 6
... ITL1 RAM MEMORY MANAGEMENT REGISTER UNIT ACCESS Host controller sub-blocks INTEGRATED RAM MEMORY P HANDLER MANAGEMENT UNIT EP HANDLER Device controller sub-blocks Rev. 03 — 23 December 2004 ISP1161A USB Interface USB STATE clock recovery PHILIPS FRAME SIE MANAGE- MENT PDT_LIST USB PROCESS TRANSCEIVER MGT930 3 ...
Page 7
... I/O bit 4 of bidirectional data; slew-rate controlled; TTL input; three-state output 5 I/O bit 5 of bidirectional data; slew-rate controlled; TTL input; three-state output Rev. 03 — 23 December 2004 ISP1161A ISP1161ABD ISP1161ABM © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 48 D_DM 47 H_PSW2 46 H_PSW1 45 DGND 44 XTAL2 ...
Page 8
... V or left unconnected. In all cases, decouple this pin to DGND DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A wants to start a DMA transfer; see DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A wants to start a DMA transfer ...
Page 9
... NDP field in the HcRhDescriptorA register; both ports will always be enabled; see (internal pull-up resistor DMA master device to inform the ISP1161A of end of DMA transfer; active level is programmable; see 35 - digital ground ‘suspend’ state indicator output; active HIGH ...
Page 10
... TTL input; three-state output 64 I/O bit 1 of bidirectional data; slew-rate controlled; TTL input; three-state output Symbol names with an overscore (e.g. NAME) represent active LOW signals. Rev. 03 — 23 December 2004 ISP1161A …continued , V reg(3.3) Table 3 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. and V . ...
Page 11
... HC and the DC. 7.5 SoftConnect The connection to the USB is accomplished by bringing D (for full-speed USB devices) HIGH through a 1.5 k pull-up resistor. In the ISP1161A DC, the 1.5 k pull-up resistor is integrated on-chip and is not connected to V connection is established through a command sent by the external or system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the USB ...
Page 12
... DC has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1161A the LED will blink off for 100 ms. During ‘suspend’ state the LED will remain off. ...
Page 13
... RAM. The EOT signal is an external end-of-transfer signal used to terminate the DMA transfer. Some microprocessors may not have this signal. In this case, the ISP1161A provides an internal EOT signal to terminate the DMA transfer as well. Setting the HcDMAConfiguration register (21H - read, A1H - write) enables the ISP1161A HC internal DMA counter for DMA transfer ...
Page 14
... Take the example of a microprocessor attempting to read the ISP1161A’s ID. The ID is kept in the HC’s HcChipID register (index 27H, read only). The 16-bit register access cycle is therefore: 1. Microprocessor writes the command code of 27H (0027H in 16-bit width) to the 2. Microprocessor reads the data word of the chip’ ...
Page 15
... Philips Semiconductors Fig 12. 16-bit register access cycle. Most of the ISP1161A internal control registers are 16 bits wide. Some of the internal control registers have 32-bit width. register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor fi ...
Page 16
... Fig 15. Accessing DC control registers. 8.4 FIFO buffer RAM access by PIO mode Since the ISP1161A internal memory is structured as a FIFO buffer RAM, the FIFO buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal FIFO buffer RAM is similar to accessing the internal control registers in multiple data phases ...
Page 17
... DACK pin (DACK1 for HC, DACK2 for DC), and at the same time, execute the DMA transfer through the data bus. In the DMA mode, the microprocessor must issue a read or write signal to the ISP1161A pin. The ISP1161A will repeat the DMA cycles until it receives an EOT signal to terminate the DMA transfer ...
Page 18
... Fig 18. DMA transfer in burst mode. In Figure 17 HIGH and DACK is active LOW. 8.6 Interrupts The ISP1161A has separate interrupt request pins for the USB HC (INT1) and the USB DC (INT2). 8.6.1 Pin configuration The interrupt output signals have four configuration modes: Mode 0 Mode 1 ...
Page 19
... INT active INT 166 ns Mode 2 edge triggered, active LOW INT active INT 166 ns Mode 3 edge triggered, active HIGH Rev. 03 — 23 December 2004 ISP1161A clear or disable INT clear or disable INT MGT944 Figure 20. © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 20
... InterruptPinEnable (bit 0 of the HcHardwareConfiguration register). In the event in which the software wishes to temporarily disable the interrupt output of the ISP1161A Host Controller, the following procedure should be followed: 1. Make sure that bit InterruptPinEnable in the HcHardwareConfiguration register is 2. Clear all bits in the Hc PInterrupt register. ...
Page 21
... ACK received for an OUT token or transmitted for an IN token. 9397 750 13962 Product data Full-speed USB single-chip host and device controller requirements. Table 81). Rev. 03 — 23 December 2004 ISP1161A Figure 21 shows the relationship between the Table 83). Default © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 22
... Bit INTENA in the DcMode register is a global enable/disable bit. Figure A INT2 pin INTENA = 0 (during this time, an interrupt event occurs. For example, SOF asserted.) Pin INT2: HIGH = de-assert; LOW = assert (individual interrupts are enabled). Rev. 03 — 23 December 2004 ISP1161A LATCH INT2 LE 22 INTENA = 0 INTENA = 1 SOF asserted SOF asserted 004aaa198 © ...
Page 23
... When an interrupt event occurs (for example, SOF interrupt) Figure 22): When bit INTENA is set to logic 1, pin INT2 is asserted Figure 22): If the firmware sets bit INTENA to logic 0, pin INT2 will still 13.3.6. Rev. 03 — 23 December 2004 ISP1161A Section 13.1.3, Section 13.1.5 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. and 23 of 134 ...
Page 24
... It is caused by the HostControllerReset field of the HcCommandStatus register (02H - read, 82H - write). 9.2 Generating USB traffic USB traffic can be generated only when the ISP1161A USB the USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState field of the HcControl register before generating USB traffi ...
Page 25
... To generate USB traffic, the HCD must enter the USB transaction loop. Prepare PTD data in P System RAM The communication between the HCD and the ISP1161A the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic information about the commands, status, and USB data packets ...
Page 26
... HC informs HCD the USB traffic results The USB transaction status and the feedback from the specified USB device endpoint will be put back into the ISP1161A HC internal FIFO buffer RAM in PTD data format. The HCD can read back the PTD data from the internal FIFO buffer RAM ...
Page 27
... Product data Full-speed USB single-chip host and device controller ActualBytes[7:0] MaxPacketSize[7:0] TotalBytes[7:0] B5_5 reserved FunctionAddress[6:0] reserved Rev. 03 — 23 December 2004 ISP1161A Active Toggle ActualBytes[9:8] Last Speed MaxPacketSize[9:8] DirectionPID[1:0] TotalBytes[9:8] © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 0 ...
Page 28
... Specifies the total number of bytes to be transferred with this data structure. For Bulk and Control only, this can be greater than MaximumPacketSize. Rev. 03 — 23 December 2004 ISP1161A Description © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 29
... This bit is logic 0 at power-on reset. When this feature is not used, software used for ISP1161A is the same for ISP1160 and ISP1161. When this bit is set to logic 1 in this PTD for interrupt endpoint transfer, only 1 PTD USB transaction will be sent out in 1 ms. ...
Page 30
... ITL1 control/bulk/interrupt ATL buffer ATL bottom Maximum number of useful data sent during one USB frame is 1280 bytes ( 1280 = 1440 bytes 150 1 = 1350 bytes. Rev. 03 — 23 December 2004 ISP1161A FIFO buffer RAM ISO_A ISO_B programmable sizes data not used 4 kbytes MGT950 © ...
Page 31
... Remark: The PTD is defined for both ATL and ITL type data transfers. For ITL, the PTD data is put into ITL buffer RAM, and the ISP1161A takes care of the Ping-Pong action for the ITL buffer RAM access. Fig 27. Buffer RAM data organization. ...
Page 32
... Operation and C program example Figure 29 mode. The ISP1161A provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port is the ITLBufferPort register (40H - read, C0H - write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H - read, C1H - write) ...
Page 33
... ITL1 buffer RAM (8-bit width) its payload data; reserved for its payload data; values beginning from incrementing by 1; with values beginning from incrementing by 2. shows the results after running this program. Rev. 03 — 23 December 2004 ISP1161A Commands Command register EOT ...
Page 34
... Set the number of bytes to be transferred HcRegWrite(wHcTransferCounter,0x50); wCount = 0x28; // Get word count outport (HcCmdPort,0x00c1); // Command for ATL buffer write 9397 750 13962 Product data Full-speed USB single-chip host and device controller Rev. 03 — 23 December 2004 ISP1161A © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 35
... HC initialized and in USBOperational state Yes Rev. 03 — 23 December 2004 ISP1161A Comments microprocessor must read ATL transfer completed transfer completed PTD data processed by HC OUT packets can be seen © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 36
... ITL0 and ITL1 are Ping-Pong structured buffers. To recover from this state, a power-on reset or software reset will have to be applied. 9397 750 13962 Product data Full-speed USB single-chip host and device controller Rev. 03 — 23 December 2004 ISP1161A Table 5). The © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 37
... AT data (frame N 1) (frame N 2) (Figure 32), the ISO part is still being written while the Start of Frame Rev. 03 — 23 December 2004 ISP1161A (frame N 3) MGT954 (frame N 3) MGT955 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 38
... Internal pull-down resistors for downstream ports There are four internal 15 k pull-down resistors built into the ISP1161A for the two downstream ports: two resistors for each port. These resistors are software selectable by programming bit 12 (2_DownstreamPort15K resistorsel) of the HcHardwareConfi ...
Page 39
... ISP1161A bit 12 HcHardware Configuration internal 004aaa088 Using either internal or external 15 k resistors. shows the ISP1161A downstream port power management scheme regulator 3 detect H_OCn H_PSWn ‘n’ represents the downstream port number ( Rev. 03 — 23 December 2004 ...
Page 40
... CC . BUS ). For the internal overcurrent detection circuit, OC DSon HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE bit 12 HcHardware Configuration 15 k ISP1161A (2 ) © Koninklijke Philips Electronics N.V. 2004. All rights reserved. . BUS to BUS ) trip of 150 m , the 004aaa090 40 of 134 ...
Page 41
... Figure 23 for the HC’s flow of USB state changes. Rev. 03 — 23 December 2004 ISP1161A HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE HcHardware Configuration ISP1161A 004aaa091 © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 42
... The ISP1161A suspend and resume clock scheme is shown in Figure Remark: The ISP1161A can only be put into a fully suspended state only after both the HC and the DC go into suspend state. At this point, the crystal can be turned off and the internal regulator can be put into power-down mode. ...
Page 43
... HC goes back into USBSuspend state. Wake-up by pin CS (software wake-up) During the USBSuspend state, an external microprocessor issues a chip select signal through pin CS. This method of access to ISP1161A internal registers is a software wake-up. Wake-up by USB devices For a USB bus resume, a USB device attached to the root hub port issues a resume signal to the HC through the USB bus, switching the HC from USBSuspend state to USBResume state ...
Page 44
... Section 10.6.4 on page 74 16 Section 10.6.5 on page 74 16 Section 10.6.6 on page 75 16 Section 10.6.7 on page 75 Rev. 03 — 23 December 2004 ISP1161A Functionality HC Control and Status registers HC Frame Counter registers HC Root Hub registers HC DMA and Interrupt Control registers HC Miscellaneous registers HC Buffer RAM Control registers © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 45
... For example, a value of 11H corresponds to version 1.1. All HC implementations that are compliant with this specification will have a value of 10H reserved R/W R reserved R/W R/W Rev. 03 — 23 December 2004 ISP1161A ...
Page 46
... USBResume state after detecting the resume signaling from a downstream port. The HC enters USBReset after a software reset and a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. - reserved Rev. 03 — 23 December 2004 ISP1161A RWE RWC 0 0 ...
Page 47
... reserved reserved R/W R reserved R/W R/W Rev. 03 — 23 December 2004 ISP1161A SOC[1: R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 48
... MasterInterruptEnable bit is set. The HCD can reserved R/W R reserved R/W R reserved R/W R/W Rev. 03 — 23 December 2004 ISP1161A R/W R/W R R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 49
... SchedulingOverrun: This bit is set when the USB schedules for current frame overruns. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented. A bit is set in the HcInterruptStatus register The corresponding bit in the HcInterruptEnable register is set The MasterInterruptEnable bit is set. Rev. 03 — 23 December 2004 ISP1161A reserved 0 ...
Page 50
... Unrecoverable Error RD 0 — ignore 1 — enable interrupt generation due to Resume Detect SF 0 — ignore 1 — enable interrupt generation due to Start of Frame - reserved SO 0 — ignore 1 — enable interrupt generation due to Scheduling Overrun Rev. 03 — 23 December 2004 ISP1161A reserved R/W R/W R ...
Page 51
... Unrecoverable Error RD 0 — ignore 1 — disable interrupt generation due to Resume Detect SF 0 — ignore 1 — disable interrupt generation due to Start of Frame - reserved SO 0 — ignore 1 — disable interrupt generation due to Scheduling Overrun Rev. 03 — 23 December 2004 ISP1161A reserved R/W R/W R ...
Page 52
... HC. Setting the HostControllerReset of the HcCommandStatus register will cause the HC to reset this field to its default value. HCD may choose to restore the saved value upon completing the Reset sequence. Rev. 03 — 23 December 2004 ISP1161A 27 26 FSMPS[14:8] 0 ...
Page 53
... HcFmInterval register at the next bit time boundary. When entering the USBOperational state, the HC reloads it with the content of the FrameInterval part of the HcFmInterval register and uses the updated value from the next SOF. Rev. 03 — 23 December 2004 ISP1161A reserved ...
Page 54
... It rolls over to 0000H after FFFFH. When the USBOperational state is entered, this field will be incremented automatically. HC will set the StartofFrame bit in the HcInterruptStatus register reserved R/W R reserved R/W R/W Rev. 03 — 23 December 2004 ISP1161A ...
Page 55
... LSThreshold: Contains a value that is compared to the FrameRemaining field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining value is calculated by the HCD, which considers transmission and set-up overhead. Default value: 1576 (628H) HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1:NDP] Rev. 03 — 23 December 2004 ISP1161A LST[10: R/W R/W ...
Page 56
... HcRhDescriptorA register: bit description Symbol Description POTPGT PowerOnToPowerGoodTime: This byte specifies the duration [7:0] HCD has to wait before accessing a powered-on port of the Root Hub. The unit of time is 2 ms. The duration is calculated as POTPGT - reserved Rev. 03 — 23 December 2004 ISP1161A R/W R/W R ...
Page 57
... NDP[1:0] NumberDownstreamPorts: These bits specify the number of downstream ports supported by the Root Hub. The maximum number of ports supported by ISP1161A is 2. Rev. 03 — 23 December 2004 ISP1161A …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 58
... When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PowerSwitchingMode = 0), this field is not valid. Bit 0 — reserved Bit 1 — Ganged-power mask on Port #1 Bit 2 — Ganged-power mask on Port #2 Rev. 03 — 23 December 2004 ISP1161A N/A N/A N/A ...
Page 59
... reserved reserved Rev. 03 — 23 December 2004 ISP1161A …continued reserved OCIC R reserved OCI ...
Page 60
... PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing logic 0 has no effect. Rev. 03 — 23 December 2004 ISP1161A © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 61
... This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes logic 1 to clear this bit. Writing logic 0 has no effect. 0 — no change in PortOverCurrentIndicator 1 — PortOverCurrentIndicator has changed Rev. 03 — 23 December 2004 ISP1161A ...
Page 62
... ClearPortPower: The HCD clears the PortPowerStatus bit by writing logic 1 to this bit. Writing logic 0 has no effect. Rev. 03 — 23 December 2004 ISP1161A …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 63
... ClearSuspendStatus: The HCD writes logic 1 to initiate a resume. Writing logic 0 has no effect. A resume is initiated only if PortSuspendStatus is set. Rev. 03 — 23 December 2004 ISP1161A …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 64
... ClearPortEnable: The HCD writes logic 1 to this bit to clear the PortEnableStatus bit. Writing logic 0 has no effect. CurrentConnectStatus is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemoveable[NDP]). Rev. 03 — 23 December 2004 ISP1161A …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 65
... Philips Semiconductors 10.4 HC DMA and interrupt control registers 10.4.1 HcHardwareConfiguration register (R/W: 20H/A0H) 1. Bit 0, InterruptPinEnable, is used as pin INT1’s master interrupt enable. This bit 2. Bits 4 and 3 are fixed at logic 0 and logic 1 for the ISP1161A. Code (Hex): 20 — read Code (Hex): A0 — write Table 36: HcHardwareConfi ...
Page 66
... DMAEnable 0 — DMA is terminated 1 — DMA is enabled This bit will be reset to zero when DMA transfer is completed - reserved Rev. 03 — 23 December 2004 ISP1161A …continued Description 0 — active LOW 1 — active HIGH. Power-up value 01 — 16 bits Others — reserved 0 — active LOW. Power-up value 1 — ...
Page 67
... R/W R Counter value R/W R/W HcTransferCounter register: bit description Symbol Description Counter The number of data bytes to be read to or written from RAM value Rev. 03 — 23 December 2004 ISP1161A …continued R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 68
... HC requires the Operational register to be updated) - reserved AllEOT 0 — no event Interrupt 1 — implies that data transfer has been completed via PIO transfer or DMA transfer. Occurrence of internal or external EOT will set this bit. Rev. 03 — 23 December 2004 ISP1161A R/W R/W R/W 3 ...
Page 69
... HC OPR Suspended Interrupt Enable Enable R/W R/W Hc PInterruptEnable register: bit description Symbol Description - reserved ClkReady 0 — power-up value 1 — enables Clkready interrupt Rev. 03 — 23 December 2004 ISP1161A …continued Section 9. R/W R/W R reserved EOT ATL Interrupt Interrupt Enable Enable ...
Page 70
... HC miscellaneous registers 10.5.1 HcChipID register (R: 27H) Read this register to get the ID of the ISP1161A silicon chip. The high byte stands for the product name (here 61H stands for ISP1161A). The low byte indicates the revision number of the product including engineering samples. ...
Page 71
... Reset[7: HcSoftwareReset register: bit description Symbol Description Reset[15:0] Writing a reset value of F6H will cause the HC to reset all the registers except its buffer memory. Rev. 03 — 23 December 2004 ISP1161A R/W R/W R R/W R/W R/W 11 ...
Page 72
... R/W R ITLBufferLength[7: R/W R/W HcITLBufferLength register: bit description Symbol Description ITLBufferLength[15:0] Assign ITL buffer length ATLBufferLength[15: R/W R/W Rev. 03 — 23 December 2004 ISP1161A 1000H (that is, 4 kbytes R/W R/W R R/W R/W R/W 1000H bytes. For example R/W R/W R/W © ...
Page 73
... Buffer read by HC ATLBuffer 0 — ATL Buffer is empty Full 1 — ATL Buffer is full ITL1Buffer 0 — 1TL1 Buffer is empty Full 1 — 1TL1 Buffer is full ITL0Buffer 0 — ITL0 Buffer is empty Full 1 — ITL0 Buffer is full Rev. 03 — 23 December 2004 ISP1161A R/W R/W R ...
Page 74
... RdITL1BufferLength[7: HcReadBackITL1Length register: bit description Symbol RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by Rev. 03 — 23 December 2004 ISP1161A Description The number of bytes for ITL0 data to be read back by ...
Page 75
... R/W R DataWord[7: R/W R/W HcITLBufferPort register: bit description Symbol Description DataWord[15:0] read/write ITL buffer RAM’s two data bytes DataWord[15: R/W R/W Rev. 03 — 23 December 2004 ISP1161A R/W R/W R R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 76
... Full-speed USB single-chip host and device controller DataWord[7: R/W R/W HcATLBufferPort register: bit description Symbol Description DataWord[15:0] read/write ATL buffer RAM’s two data bytes. Rev. 03 — 23 December 2004 ISP1161A R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved R 134 ...
Page 77
... DC data transfer operation The following session explains how the ISP1161A handles an IN data transfer and an OUT data transfer. In the Device mode, ISP1161A acts as a USB device data transfer means transfer from ISP1161A to an external USB Host (through the upstream port) and an OUT transfer means transfer from external USB Host to ISP1161A ...
Page 78
... DcEndpointStatus register. If the buffer is full, it empties the buffer, so that data can be received by the SIE at the next OUT token phase. the DMA count is complete DMAEN = 0 the DMA controller asserts EOT. Rev. 03 — 23 December 2004 ISP1161A © Koninklijke Philips Electronics N.V. 2004. All rights reserved 134 ...
Page 79
... The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] IN: input for the USB host (ISP1161A transmits); OUT: output from the USB host (ISP1161A receives). The data flow direction is determined by bit EPDIR in the DcEndpointConfiguration register; see 11 ...
Page 80
... Endpoint description control IN (64 byte fixed) control OUT (64 byte fixed) double-buffered 1023-byte isochronous endpoint 16-byte interrupt OUT 16-byte interrupt IN double-buffered 64-byte bulk OUT double-buffered 64-byte bulk IN © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1161A 80 of 134 ...
Page 81
... IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or via the USB bus, the ISP1161A’s DC disables all endpoints and clears all ECRs, except for the control endpoint which is fixed and always enabled. Endpoint initialization can be done at any time ...
Page 82
... All signals connected to the ISP1161A DC must enter appropriate states to meet the power consumption requirements of the suspend state. b. All input pins of the ISP1161A DC must have a CMOS LOW or HIGH level. USB bus. When bit BUSTATUS in the DcInterrupt register is logic 0, the USB bus has left the suspend mode and the process must be aborted. Otherwise, the next step can be executed ...
Page 83
... B: indicates resume condition, which can K-state on the USB bus, a HIGH level on pin D_WAKEUP LOW level on pin CS. • C: indicates remote wake-up. The ISP1161A will drive a K-state on the USB bus for 10 ms after pin D_WAKEUP goes HIGH or pin CS goes LOW. • ...
Page 84
... The SUSPEND output is deasserted, and bit RESUME in the DcInterrupt register 3. Maximum 15 ms after starting the wake-up sequence, the ISP1161A case of a remote wake-up, the ISP1161A DC drives a K-state on the USB bus 5. Following the deassertion of output SUSPEND, the application restores itself and 6 ...
Page 85
... Many different implementations of DMA exist. The ISP1161A DC supports two methods: • • ISP1161A’s DC supports DMA transfer for all 14 configurable endpoints (see Table operation of ISP1161A’s DC can be interleaved with normal I/O mode access to other endpoints. The following features are supported: • • • ...
Page 86
... It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of ISP1161A’ 8237 compatible DMA mode is given in The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge) ...
Page 87
... After completing the current instruction cycle, the CPU places the bus control 5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR 6. The 8237 asserts DACK to inform ISP1161A’s DC that it will start a DMA transfer. 7. ISP1161A’s DC now places the word to be transferred on the data bus lines, 8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This 9. ISP1161A’ ...
Page 88
... EOT DACK-only mode ISP1161A’s DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes. Fig 41. ISP1161A’ ...
Page 89
... An End-Of-Packet (EOP) signal is detected DMA operation is disabled by clearing bit DMAEN. Recommended EOT usage for isochronous endpoints OUT endpoint do not use do not use preferred Rev. 03 — 23 December 2004 ISP1161A IN endpoint EOT is active transfer completes as programmed in the DcDMACounter register counter reaches zero in the middle of the buffer ...
Page 90
... Philips Semiconductors 13. DC commands and registers The functions and registers of ISP1161A’s DC are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in A complete access consists of two phases: 1 ...
Page 91
... Endpoint DcEndpointStatusImage register endpoint 0 OUT DcEndpointStatusImage register endpoint 0 IN DcEndpointStatusImage register n endpoint Endpoint 0 IN and OUT DcErrorCode register endpoint 0 OUT DcErrorCode register endpoint 0 IN Rev. 03 — 23 December 2004 ISP1161A [1] Code (Hex) Transaction (00 bytes isochronous: N interrupt/bulk ...
Page 92
... Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of ISP1161A’s DC and to perform a device reset. 13.1.1 DcEndpointConfiguration register (R/W: 30H–3FH/20H–2FH) This command is used to access the DcEndpointConfi ...
Page 93
... DcMode register (R/W: B9H/B8H) This command is used to access the ISP1161A’s DcMode register, which consists of 1 byte (for bit allocation: see The DcMode register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt. Code (Hex): B8/B9 — ...
Page 94
... Bus reset value: unchanged. - reserved SOFTCT Logic 1 enables SoftConnect (see ignored if EXTPUL = 1 in the DcHardwareConfiguration register (see Table NOLAZY CLKRUN R/W R/W Rev. 03 — 23 December 2004 ISP1161A INTENA DBGMOD reserved [1] [1] [ R/W R/W R/W Section 8.6.3. Section 7.5). This bit is 82) ...
Page 95
... Selects the interrupt signalling mode on output pin INT2 (0 = level pulsed). In pulsed mode an interrupt produces an 166 ns pulse. See Bus reset value: unchanged. INTPOL Selects INT2 pin signal polarity (0 = active LOW active HIGH). Bus reset value: unchanged. Rev. 03 — 23 December 2004 ISP1161A 3 2 WKUPCS PWROFF INTLVL 0 0 ...
Page 96
... INT2 pin interrupt event occurs Pin INT2: HIGH = de-assert; LOW = assert; INTENA = 1. Table 29 28 reserved R/W R IEP12 IEP11 R/W R/W Rev. 03 — 23 December 2004 ISP1161A DcInterruptEnable register enabled interrupt is cleared interrupt event 004aaa197 occurs 84. Section 8.6. R/W R/W R IEP10 IEP9 IEP8 ...
Page 97
... DcDMAConfiguration register (R/W: F1H/F0H) This command defines the DMA configuration of ISP1161A’s DC and enables/disables DMA transfers. The command accesses the DcDMAConfiguration register, which consists of 2 bytes. The bit allocation is given in will clear bit DMAEN (DMA disabled), all other bits remain unchanged. ...
Page 98
... Bus reset value: unchanged. 88. Writing to the register sets the number of bytes for a DMA transfer. Reading DMACR[15: R/W R DMACR[7: R/W R/W Rev. 03 — 23 December 2004 ISP1161A Section 11.2. Section 13.1.6 for more details R/W R/W R R/W R/W R/W © ...
Page 99
... Table 89: Bit 13.1.8 Reset Device (F6H) This command resets the ISP1161A DC in the same way as an external hardware reset via input RESET. All registers are initialized to their ‘reset’ values. Code (Hex): F6 — reset the device Transaction — none 13.2 Data flow commands Data fl ...
Page 100
... Reading the DcEndpointStatus register will clear the interrupt bit set for the 13.2.3 EPFULL0 DATA_PID Rev. 03 — 23 December 2004 ISP1161A Word # Description - command code (00H to 1FH) - ignored 0 packet length 1 data word 1 (data byte 2, data byte 1) 2 data word 2 (data byte 4, data byte 3) … ...
Page 101
... Logic 1 indicates that the buffer contains a Setup packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 03 — 23 December 2004 ISP1161A Table 92). Section 11.3.6. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 101 of 134 ...
Page 102
... Setup packet. SETUPT Logic 1 indicates that the buffer contains a Setup packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 03 — 23 December 2004 ISP1161A Section OVER SETUPT CPUBUF WRITE 0 ...
Page 103
... PID encoding error; bits are not the inverse of bits PID unknown; encoding is valid, but PID does not exist unexpected packet; packet is not of the expected type (token, data, or acknowledge SETUP token to a non-control endpoint token CRC error data CRC error Rev. 03 — 23 December 2004 ISP1161A Section ERROR[3:0] 0 ...
Page 104
... Unlock Device (B0H) This command unlocks ISP1161A’s DC from write-protection mode after a ‘resume’. In ‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption by external devices during a ‘resume’. Also, the register access for reading is possible only after the ‘Unlock Device’ command is executed. ...
Page 105
... SOFRL[7: Symbol Description - reserved SOFRH[2:0] SOF frame number (part of upper byte) SOFRL[7:0] SOF frame number (lower byte) Rev. 03 — 23 December 2004 ISP1161A SFIRH[4: R/W R/W R R/W R/W R/W Table 103 SOFRH[2:0] ...
Page 106
... CHIPIDL[7: Symbol Description CHIPIDH[7:0] chip ID code (61H) CHIPIDL[7:0] silicon version (22H) Table Section 13.1.5. Rev. 03 — 23 December 2004 ISP1161A Word # Description - command code (B4H) - ignored 0 frame number 108 ...
Page 107
... SUSPND Logic 1 indicates that an ‘awake’ to ‘suspend’ change of state was detected on the USB bus. RESUME Logic 1 indicates that a ‘resume’ state was detected. RESET Logic 1 indicates that a bus reset condition was detected. Rev. 03 — 23 December 2004 ISP1161A ...
Page 108
... D_DP port connector Fig 43. Using supply. 9397 750 13962 Product data Full-speed USB single-chip host and device controller Figure 43. ISP1161A has an internal DC/DC regulator to provide 3.3 V for Figure 44. If, however, you have board space (routing area USB upstream port connector ...
Page 109
... Philips Semiconductors 15. Crystal oscillator and LazyClock The ISP1161A has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open. See Figure ISP1161A CLKOUT XTAL2 XTAL1 Fig 45. Oscillator circuit with external crystal. ...
Page 110
... NOLAZY Fig 47. Oscillator and LazyClock logic. When ISP1161A’s DC enters ‘suspend’ state (by setting and clearing bit GOSUSP in the DcMode register), outputs D_SUSPEND and CLKOUT change state after approximately 2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT does not stop, but changes to the 100 kHz When resuming from ‘ ...
Page 111
... Product data Full-speed USB single-chip host and device controller Conditions pin pin V < > < Conditions with internal regulator internal regulator bypass Rev. 03 — 23 December 2004 ISP1161A Min Max 0.5 6.0 0.5 +4.6 0.5 +6.0 - 100 CC [1] - 2000 60 150 Min Typ 4 ...
Page 112
... unless otherwise specified. GND amb Conditions = unless otherwise specified. GND amb Conditions [ pin to GND Rev. 03 — 23 December 2004 ISP1161A Min Typ Max [1] 3.0 3.3 3 500 - ...
Page 113
... unless otherwise specified. GND amb Conditions V V I(D ) I(D ) includes V range 1 3 GND L pin to GND enable internal resistors SoftConnect = ON steady-state drive ) both H_D and H_D . Rev. 03 — 23 December 2004 ISP1161A Min Typ Max [1] 0 0 0.8 2 0.3 2 ...
Page 114
... Conditions crystal oscillator running crystal oscillator stopped [ GND amb Conditions pF pF Rev. 03 — 23 December 2004 ISP1161A Min Typ Max 160 - - [ 100 - 500 ...
Page 115
... If you are accessing only the HC, then the HC Programmed I/O timing applies. If you are accessing only the DC, then the DC Programmed I/O timing applies. If you are accessing both the HC and the DC, then the DC Programmed I/O timing applies. Conditions Rev. 03 — 23 December 2004 ISP1161A Min Typ Max 5 - ...
Page 116
... CS SHDZ HIGH t chip deselect after RD HIGH RHSH t RD pulse width RLRH t data valid time after RD LOW RLDV t CS HIGH until next ISP1161A RD SHRL read cycle time SHRL RLRH Write timing (see Figure 51) t address hold time after WR HIGH WHAX ...
Page 117
... Full-speed USB single-chip host and device controller Conditions t RHAX t AVRL t SHDZ (1) t RLRH t SHRL t RHSH t WHAX t AVWL t WLWH (1) t SHWL t WHSH t WHDZ Rev. 03 — 23 December 2004 ISP1161A …continued Min Typ Max 004aaa105 004aaa106 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 118
... Fig 52. HC single-cycle DMA timing. 9397 750 13962 Product data Full-speed USB single-chip host and device controller Conditions ALRL t RHAL t RLDV t RHDZ data valid data valid t WSU t WHD Rev. 03 — 23 December 2004 ISP1161A Min Typ Max ...
Page 119
... Fig 53. HC burst mode DMA timing. 9397 750 13962 Product data Full-speed USB single-chip host and device controller Conditions 4-cycle burst mode 8-cycle burst mode 4-cycle burst mode 8-cycle burst mode t RHRL RLRH Rev. 03 — 23 December 2004 ISP1161A Min Typ Max 102 - - ...
Page 120
... Full-speed USB single-chip host and device controller DREQ1 DACK1 EOT t RLIS 0 ns DREQ1 DACK1 EOT t RLIS 0 ns Conditions ASRP Rev. 03 — 23 December 2004 ISP1161A 004aaa109 004aaa110 Min Typ Max - - 40 180 - - 004aaa111 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Unit ns ns ...
Page 121
... Product data Full-speed USB single-chip host and device controller Conditions Min - 25 180 - - t ASRP t ASAP t APDZ t ASDV Conditions Min - 180 ASAP t ASRP t ASDV Rev. 03 — 23 December 2004 ISP1161A Typ Max Unit - APRS 004aaa112 Typ Max Unit ...
Page 122
... DMA burst repeat interval (input IHIL RD/WR HIGH to LOW) 9397 750 13962 Product data Full-speed USB single-chip host and device controller Conditions EOT on; DACK on; RD/WR LOW t RSIH t ASRP t IHAP (1) t RLIS t EOT t WLIS (3) Conditions Rev. 03 — 23 December 2004 ISP1161A Min Typ Max 004aaa114 Min ...
Page 123
... Fig 61. EOT timing in DC burst mode DMA. 9397 750 13962 Product data Full-speed USB single-chip host and device controller t RSIH t IHIL Conditions EOT on; DACK on; RD/WR LOW t ISRP t RLIS t WLIS (1) t EOT Rev. 03 — 23 December 2004 ISP1161A t ILRP t IHAP 004aaa115 Min Typ Max ...
Page 124
... Two address lines A1 and A0 are needed for a complete addressing of the ISP1161A internal registers: • The CS line is used for chip selection of ISP1161A in a certain address range of the RISC system. This signal is active LOW. 9397 750 13962 Product data Full-speed USB single-chip host and device controller ...
Page 125
... DC/DC regulator will be bypassed best to connect all four power supply pins (V CC Section ISP1161A the flexibility to be used in an embedded system under either a 3 power supply. A typical SH7709 interface circuit is shown in 19.3 Typical software model This section shows a typical software requirement for an embedded system that incorporates ISP1161A ...
Page 126
... MASS STORAGE CLASS DRIVER PRINTING CLASS DRIVER RISC ROM RAM LEN CONTROL Fig 63. ISP1161A software model for DSC application. 20. Test information The dynamic characteristics of the analog I/O ports (D and D Table 116 Fig 64. Load impedance for D_DP and D_DM pins. 9397 750 13962 Product data ...
Page 127
... REFERENCES JEDEC JEITA MS-026 Rev. 03 — 23 December 2004 detail 0.75 1.45 1 0.2 0.12 0.1 0.45 1.05 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1161A SOT314 ( 1.05 0 ISSUE DATE 00-01-19 03-02-25 127 of 134 ...
Page 128
... JEDEC JEITA MS-026 Rev. 03 — 23 December 2004 detail 9.15 0.75 0.64 1 0.2 0.08 0.08 8.85 0.45 0.36 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1161A SOT414 ( 0.36 0 ISSUE DATE 00-01-19 03-02-20 128 of 134 ...
Page 129
... C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. Rev. 03 — 23 December 2004 ISP1161A 2.5 mm 350 called small/thin packages. ...
Page 130
... Circuit Packages; Section: Packing Methods . Rev. 03 — 23 December 2004 Soldering method Wave not suitable [4] not suitable suitable [5][6] not recommended [7] not recommended [8] not suitable © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1161A [2] Reflow suitable suitable suitable suitable suitable not suitable 130 of 134 ...
Page 131
... The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. Rev. 03 — 23 December 2004 ISP1161A 10 C measured in the atmosphere of the reflow © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 131 of 134 ...
Page 132
... RHAX t . SHWL Product data (9397 750 10772) Product data (9397 750 09568) Rev. 03 — 23 December 2004 ISP1161A circuit”: fourth paragraph, second timing”: changed the from ns, and added t WHAX © Koninklijke Philips Electronics N.V. 2004. All rights reserved. and ...
Page 133
... MIPS-based — trademark of MIPS Technologies, Inc. SoftConnect — trademark of Koninklijke Philips Electronics N.V. StrongARM — registered trademark of ARM Ltd. SuperH — trademark of Hitachi Ltd. Rev. 03 — 23 December 2004 ISP1161A Fax: + 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 133 of 134 ...
Page 134
... Static characteristics . . . . . . . . . . . . . . . . . . 112 18 Dynamic characteristics . . . . . . . . . . . . . . . . 114 18.1 Programmed I/O timing . . . . . . . . . . . . . . . . 115 18.2 DMA timing 118 19 Application information . . . . . . . . . . . . . . . . 124 19.1 Typical interface circuit . . . . . . . . . . . . . . . . . 124 19.2 Interfacing a ISP1161A with a SH7709 RISC processor 124 19.3 Typical software model . . . . . . . . . . . . . . . . . 125 20 Test information 126 21 Package outline . . . . . . . . . . . . . . . . . . . . . . . 127 22 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 22.1 Introduction to soldering surface mount packages ...