SC1100UFH-266 National Semiconductor, SC1100UFH-266 Datasheet
SC1100UFH-266
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SC1100UFH-266 Summary of contents
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... Bus I/F GPIO Audio Codec I/F LPC I/F National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode and VSA are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks. © 2003 National Semiconductor Corporation • SuperI/O module - Has a Serial Port (UART), an Infrared (IR) interface, two ACCESS ...
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Features General Features 32-bit x86 processor 300 MHz, with MMX instruc- tion set support Memory controller with 64-bit SDRAM interface PC/AT functionality PCI bus controller IDE interface, two channels USB, three ports, OHCI (OpenHost Controller Interface) version 1.0 ...
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SuperI/O Module Real-Time Clock (RTC): — DS1287, MC146818 and PC87911 compatible — Multi-century calendar ACCESS.bus (ACB) Interface: — Two ACB interface ports Serial Port (UART): — Enhanced UART Infrared (IR) Port — IrDA1.1 and 1.0 compatible — Sharp-IR options ASK-IR ...
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Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents (Continued) 3.0 General Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents (Continued) 4.6 SYSTEM WAKEUP CONTROL (SWC ...
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Table of Contents (Continued) 5.2.8 Keyboard Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents (Continued) 7.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Architecture Overview As illustrated in Figure 1-1, the SC1100 contains the follow- ing modules in one integrated device: • GX1 Module: — Combines advanced CPU performance with MMX support, a 64-bit synchronous DRAM (SDRAM) inter- face and a PCI ...
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Architecture Overview (Continued) 1.1 GX1 MODULE The GX1 module (based upon silicon revision 8.1.1) is the central module of the SC1100. For detailed information regarding the GX1 module, refer to the Geode GX1 Pro- cessor Series datasheet and the Geode ...
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Architecture Overview (Continued) 1.1.1 Integer Unit The integer unit consists of: • Instruction Buffer • Instruction Fetch • Instruction Decoder and Execution The pipelined integer unit fetches, decodes, and executes x86 instructions through the use of a five-stage integer pipeline. ...
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Architecture Overview (Continued) 1.1.6 Integrated Functions The GX1 module integrates the following functions tradi- tionally implemented using external devices: • SDRAM memory controller • PCI bridge The module has also been enhanced to support VSA tech- nology implementation. 1.1.6.1 Memory ...
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Architecture Overview (Continued) 1.1.7.3 Slave PCI Burst Length Control The name of this bit differs from that described in the GX1 Processor Series datasheet. There called SDBE. Oth- erwise, the functionality is the same as the standalone GX1 ...
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Architecture Overview (Continued) 1.2 CORE LOGIC MODULE The Core Logic module is described in detail in Section 5.0 "Core Logic Module" on page 116. The Core Logic module is connected to the Fast-PCI bus. It uses signal AD28 as the ...
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Architecture Overview (Continued) 1.4.1.1 Power-On Reset Power-on reset is triggered by assertion of the POR# sig- nal. Upon power-on reset, the following things happen: • Strap pins are sampled. • PLL4, FMUL3, PLL5 are reset, disabling their output. When the ...
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Signal Definitions This section defines the signals and describes the external interface of the SC1100. Figure 2-1 shows the signals organized by their functional groups. Where signals are multiplexed, the default signal name is listed first and is POR# ...
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Signal Definitions (Continued) The remaining subsections of this chapter describe: • Section 2.1 "Ball Assignments": Provides a ball assign- ment diagram and tables listing the signals sorted according to ball number and alphabetically by signal name. • Section 2.2 "Strap ...
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Signal Definitions (Continued CS1# MD17 MD19 MD21 MD23 CS0# MD16 MD18 MD20 MD22 MD52 RASA# WEA# V SDCKO SDCK1 MD49 MD51 MD53 ...
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Signal Definitions (Continued) Table 2-2. Ball Assignment - Sorted by Ball Number 1 Ball I/O Buffer No. Signal Name (PU/PD) Type A1 V GND --- PWR --- IO A3 CS1 2/5 2 MD17 I/O IN ...
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Signal Definitions (Continued) Table 2-2. 1 Ball I/O Buffer No. Signal Name (PU/PD) Type 2 MD53 I 2/5 2 MD55 I 2/5 C10 MA7 O O 2/5 C11 BA0 O ...
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Signal Definitions (Continued) Table 2-2. 1 Ball I/O Buffer No. Signal Name (PU/PD) Type E26 GPIO32 I PCI ( 22.5 PCI LAD0 I PCI ( 22.5 PCI 2 MD12 I ...
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Signal Definitions (Continued) Table 2-2. 1 Ball I/O Buffer No. Signal Name (PU/PD) Type L23 V PWR --- CORE L24 AD20 I PCI O PCI A20 O O PCI L25 SERR# I PCI ( ...
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Signal Definitions (Continued) Table 2-2. 1 Ball I/O Buffer No. Signal Name (PU/PD) Type 2 MD2 I 2/5 2 MD36 I 2/5 2 MD37 I ...
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Signal Definitions (Continued) Table 2-2. 1 Ball I/O Buffer No. Signal Name (PU/PD) Type AA24 GPIO41 I ( 22.5 2/5 TEST0 O O 2/5 (PU ) 22.5 F_C/BE0 1/4 (PU ) 22.5 AA25 ...
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Signal Definitions (Continued) Table 2-2. 1 Ball I/O Buffer No. Signal Name (PU/PD) Type AD10 FMUL3B I 2/5 TEST1 O O 2/5 AD11 SIN F_C/BE1 1/4 AD12 GPIO6 I ...
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Signal Definitions (Continued) Table 2-2. 1 Ball I/O Buffer No. Signal Name (PU/PD) Type AE22 SYNC O O 2/5 CLKSEL3 (PD ) 100 AE23 GPIO12 I ( 22.5 2/8 AB2C I/O IN ...
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Signal Definitions (Continued) Table 2-3. Ball Assignment - Sorted Alphabetically by Signal Name Signal Name Ball No. A0 E25 A1 F26 A2 F25 A3 G26 A4 G25 A5 H26 H25 A6 D24 A7 A8 E23 A9 J26 A10 J25 A11 ...
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Signal Definitions (Continued) Table 2-3. Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. DTR#/BOUT AD12 F_AD0 AC24 F_AD1 Y1 F_AD2 Y2 F_AD3 AE23 F_AD4 AD23 F_AD5 AB23 F_AD6 B20 F_AD7 AB24 F_C/BE0# AA24 F_C/BE1# AD11 ...
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Signal Definitions (Continued) Table 2-3. Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. MA2 K1 MA3 M3 MA4 L3 MA5 K3 MA6 A8 MA7 C10 MA8 A9 MA9 B10 MA10 A10 MA11 C13 MA12 D2 ...
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Signal Definitions (Continued) Table 2-3. Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. SIN AD11 SMI_O AC12 SOUT AE11 STOP# M25 SYNC AE22 TCK AE20 TDI AF20 TDO AD20 TEST0 AA24 TEST1 AD10 TEST2 AC11 ...
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Signal Definitions (Continued) 2.2 STRAP OPTIONS Several balls are read at power-up that set up the state of the SC1100. These balls are typically multiplexed with other functions that are outputs after the power-up sequence is complete. The SC1100 must ...
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Signal Definitions (Continued) 2.3 MULTIPLEXING CONFIGURATION The tables that follow list multiplexing options and their configurations. Certain multiplexing options may be chosen per signal; others are available only for a group of signals. A pull-up resistor is optional on the ...
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Signal Definitions (Continued) Table 2-5. Two-Signal/Group Multiplexing (Continued) Ball No. Signal --- AC97, GPIO, ACB, UART AF23 AC97_RST# AF22 4 SDATA_IN AC22 5 BIT_CLK AD24 GPIO1 AD11 6 SIN AC24 GPIO18 Y1 7 AB1C Y2 7 AB1D AB23 GPIO38 AB24 ...
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Signal Definitions (Continued) Table 2-6. Three-Signal/Group Multiplexing Default Ball No. Signal Configuration --- Sub-ISA C22 IOW# PMR[ and PMR[21 --- Infrared C20 IRTX PMR[ and PMR[29 --- GPIO B23 GPIO17 PMR[5] = ...
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Signal Definitions (Continued) Table 2-7. Four-Signal /Group Multiplexing Default Ball No. Signal Configuration --- GPIO D22 GPIO14 PMR[ and PMR[21 --- Infrared AE18 1 PMR[ IRRX1 PMR[ and PMR[27 and ...
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Signal Definitions (Continued) 2.4 SIGNAL DESCRIPTIONS Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identi- cal information. 2.4.1 System Interface Signal Name Ball No. Type CLKSEL1 AD25 CLKSEL0 D23 CLKSEL3 AE22 ...
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Signal Definitions (Continued) 2.4.1 System Interface (Continued) Signal Name Ball No. Type PCIRST# M26 2.4.2 Memory Interface Signals Signal Name Ball No. Type MD[63:0] See Table 2-3 on page 27 MA[12:0] See Table 2-3 on page 27 BA1 C12 BA0 ...
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Signal Definitions (Continued) 2.4.2 Memory Interface Signals (Continued) Signal Name Ball No. Type SDCLK3 A17 SDCLK2 A16 SDCLK1 C5 SDCLK0 E4 SDCLK_IN D4 SDCLK_OUT C4 2.4.3 ACCESS.bus Interface Signals Signal Name Ball No. Type AB1C Y1 AB1D Y2 AB2C AE23 ...
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Signal Definitions (Continued) 2.4.4 PCI Bus Interface Signals (Continued) Signal Name Ball No. Type C/BE3# V26 C/BE2# R26 C/BE1# G24 C/BE0# E24 INTA# AD26 INTB# W24 INTC# Y24 INTD# V24 PAR H24 FRAME# P25 IRDY# P26 TRDY# N25 Revision 1.1 ...
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Signal Definitions (Continued) 2.4.4 PCI Bus Interface Signals (Continued) Signal Name Ball No. Type STOP# M25 DEVSEL# N26 PERR# J24 SERR# L25 REQ3# T24 REQ2# AC26 REQ1# AA25 REQ0# AA26 GNT3# AC25 GNT2# U24 GNT1# AD25 GNT0# AB26 www.national.com Description ...
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Signal Definitions (Continued) 2.4.5 Sub-ISA Interface Signals Signal Name Ball No. A[23:0] See Table 2-3 on page 27 D15 M25 D14 P26 D13 N25 D12 H24 D11 V26 D10 R26 D9 G24 D8 E24 D[7:0] Y25, R24, Y26, W25, P24, ...
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Signal Definitions (Continued) 2.4.6 Low Pin Count (LPC) Bus Interface Signals Signal Name Ball No. Type LAD[3:0] C25, D26, D25, E26 LDRQ# C26 LFRAME# B24 SERIRQ A24 2.4.7 IDE Interface Signals Signal Name Ball No. Type IDE_RST# AD6 IDE_ADDR[2:0] Y3, ...
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Signal Definitions (Continued) 2.4.8 Universal Serial Bus (USB) Interface Signals Signal Name Ball No. Type POWER_EN AD19 OVER_CUR# AE19 DPOS_PORT1 AD7 DNEG_PORT1 AE7 DPOS_PORT2 AF7 DNEG_PORT2 AF8 DPOS_PORT3 AD8 DNEG_PORT3 AE8 2.4.9 Serial Port (UART) and Infrared (IR) Interface Signals ...
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Signal Definitions (Continued) 2.4.9 Serial Port (UART) and Infrared (IR) Interface Signals (Continued) Signal Name Ball No. Type DCD# AE12 DSR# AF12 IRRX1 AE18 IRTX C20 2.4.10 AC97 Audio Interface Signals Signal Name Ball No. Type BIT_CLK AC22 SDATA_OUT AD22 ...
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Signal Definitions (Continued) 2.4.11 Power Management Interface Signals (Continued) Signal Name Ball No. Type PWRBTN# AF15 PWRCNT1 AE17 PWRCNT2 AF18 THRM# AE15 2.4.12 GPIO Interface Signals Name Ball No. Type GPIO0 B22 I/O GPIO1 AD24 GPIO2 B21 GPIO3 A22 GPIO6 ...
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Signal Definitions (Continued) 2.4.12 GPIO Interface Signals Name Ball No. Type GPIO32 E26 I/O GPIO33 D25 GPIO34 D26 GPIO35 C25 GPIO36 C26 GPIO37 B24 GPIO38 AB23 GPIO39 A24 GPIO40 B20 GPIO41 AA24 GPIO47 AB24 2.4.13 Debug Monitoring Interface Signals Signal ...
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Signal Definitions (Continued) 2.4.13 Debug Monitoring Interface Signals (Continued) Signal Name Ball No. Type SMI_O AC12 O 2.4.14 JTAG Interface Signals Signal Name Ball No. Type TCK AE20 TDI AF20 TDO AD20 TMS AF21 TRST# AC20 2.4.15 Test and Measurement ...
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Signal Definitions (Continued) 2.4.15 Test and Measurement Interface Signals (Continued) Signal Name Ball No. GTEST AD21 1 2.4.16 Power , Ground and No Connections Signal Name Ball No. AV AF9 SSPLL AV AF6 CCUSB AV AD9 SSUSB V W3 BAT ...
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General Configuration Block The General Configuration Block (GCB) includes registers for: • Pin Multiplexing and Miscellaneous Configuration • WATCHDOG Timer • High-Resolution Timer • Clock Generators A selectable interrupt is shared by all these functions. 3.1 CONFIGURATION BLOCK ADDRESSES ...
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General Configuration Block 3.2 MULTIPLEXING, INTERRUPT SELECTION, AND BASE ADDRESS REGISTERS The registers described in the Table 3-2 are used to deter- mine general configuration for the Geode SC1100. These registers also indicate which multiplexed signals are issued via balls ...
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General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 25 AC97CKEN (Enable AC97_CLK Output). This bit enables the output drive of AC97_CLK (ball AC21). 0: AC97_CLK output is HiZ. 1: AC97_CLK output is enabled. ...
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General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 14 LPCSEL (Select LPC Bus). Selects ball functions. 0: GPIO Signal Ball # Name E26 GPIO32 D25 GPIO33 D26 GPIO34 C25 GPIO35 C26 GPIO36 B24 ...
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General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description Offset 34h Miscellaneous Configuration Register - MCR (R/W) Width: DWORD Power-on reset value: The BOOT16 strap pin selects "Enable 16-Bit Wide Boot Memory". 31 Reserved. ...
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General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 4 IRTXEN (Infrared Transmitter Enable). This bit enables the drive of Infrared transmitter’s output. 0: IRTX+GXCLK+TEST3 line (ball C20) is HiZ. 1: IRTX+GXCLK+TEST3 line (ball ...
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General Configuration Block 3.3 WATCHDOG The SC1100 includes a WATCHDOG function to serve as a fail-safe mechanism in case the system becomes hung. When triggered, the WATCHDOG mechanism returns the system to a known state by generating an interrupt, an ...
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General Configuration Block WATCHDOG Interrupt The WATCHDOG interrupt (if configured and enabled) is routed to an IRQ signal. The IRQ signal is programmable via the INTSEL register (Offset 38h, described in Table 3-2 "Multiplexing, Interrupt Selection, and Base Address Regis- ...
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General Configuration Block Table 3-3. WATCHDOG Registers (Continued) Bit Description Offset 04h Width: Byte This register contains WATCHDOG status information. 7:4 Reserved. Write as read. 3 WDRST (WATCHDOG Reset Asserted). (Read Only) This bit is set to 1 when WATCHDOG ...
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General Configuration Block Table 3-4. High-Resolution Timer Registers Bit Description Offset: 08h Width: DWORD This register contains the current value of the High-Resolution Timer. 31:0 Current Timer Value. Offset: 0Ch Width: Byte This register supplies the High-Resolution Timer status information. ...
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General Configuration Block 3.5 CLOCK GENERATORS AND PLLS This section describes the registers for the clocks required by the GX1 and Core Logic modules, and how these clocks are generated. See Figure 3-2 for a clock generation dia- gram. 32.768 ...
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General Configuration Block 3.5.1 27 MHz Crystal Oscillator The internal oscillator employs an external crystal con- nected to the on-chip amplifier. The on-chip amplifier is accessible on the X27I input (ball AF10) and the X27O out- put (ball AE10) signals. ...
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General Configuration Block 3.5.2 GX1 Module Core Clock The core clock is generated by an Analog Delay Loop (ADL) clock generator from the internal Fast-PCI clock. The clock can be any whole-number multiple of the input clock between 4 and ...
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General Configuration Block 3.5.4 SuperI/O Clocks The SuperI/O module requires a 48 MHz input to the UART and other functions. This clock is supplied by PLL4 using a multiplier value of 576/(108x3) to generate 48 MHz. 3.5.5 Core Logic Module ...
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General Configuration Block 3.5.6 Clock Registers Bit Description Offset: 10h Maximum Core Clock Multiplier Register - MCCM (RO) Width: Byte This register holds the maximum core clock multiplier value. The maximum clock frequency allowed by the core, is the Fast-PCI ...
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General Configuration Block Table 3-8. Clock Generator Configuration (Continued) Bit Description Offset: 1Eh Core Clock Frequency Control Register - CCFC (R/W) Width: WORD This register controls the configuration of the core clock multiplier and the reference clocks. 15:14 Reserved. Write ...
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SuperI/O Module The SuperI/O (SIO) module is a member of National Semi- conductor’s SuperI/O family of integrated PC peripherals PC98 and ACPI compliant SIO that offers a single-cell solution to the most commonly used ISA peripherals. ...
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SuperI/O Module (Continued) 4.1 FEATURES PC98 and ACPI Compliant • PnP Configuration Register structure • Flexible resource allocation for all logical devices: — Relocatable base address — 9 parallel IRQ routing options — 3 optional 8-bit DMA channels (where applicable) ...
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SuperI/O Module (Continued) 4.2 MODULE ARCHITECTURE The SIO module comprises a collection of generic func- tional blocks. Each functional block is described in detail later in this chapter. The beginning of this chapter describes the SIO structure and provides all ...
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SuperI/O Module (Continued) 4.3 CONFIGURATION STRUCTURE / ACCESS This section describes the structure of the configuration register file, and the method of accessing the configuration registers. 4.3.1 Index-Data Register Pair The SIO configuration access is performed via an Index- Data ...
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SuperI/O Module (Continued) Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a non- existing register or the LDN is higher than 08h), are ignored and a read returns 00h on all addresses ...
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SuperI/O Module (Continued) 4.4 STANDARD CONFIGURATION REGISTERS As illustrated in Figure 4-4, the Standard Configuration reg- isters are broadly divided into two categories: SIO Control and Configuration registers and Logical Device Control and Configuration registers (one per logical device, some ...
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SuperI/O Module (Continued) Table 4-3 provides the bit definitions for the Standard Con- figuration registers. • All reserved bits return 0 on reads, except where noted otherwise. They must not be modified as such modifica- tion may cause unpredictable results. ...
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SuperI/O Module (Continued) Table 4-3. Standard Configuration Registers (Continued) Bit Description Index 74h Width: Byte Selected DMA channel for DMA 0 of the logical device (0 - the first DMA channel when using more than one DMA channel). 7:3 Reserved. ...
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SuperI/O Module (Continued) 4.4.1 SIO Control and Configuration Registers Table 4-4 lists the SIO Control and Configuration registers and Table 4-5 provides their bit formats. Table 4-4. SIO Control and Configuration Register Map Index Type Name 20h RO SID. SIO ...
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SuperI/O Module (Continued) 4.4.2 Logical Device Control and Configuration As described in Section 4.3.2 "Banked Logical Device Reg- isters" on page 68, each functional block is associated with a Logical Device Number (LDN). This section provides the register descriptions for ...
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SuperI/O Module (Continued) Bit Description Index F0h Width: Byte When any non-reserved bit in this register is set can be cleared only by hardware reset. 7 Block Standard RAM effect on Standard RAM access. (Default) ...
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SuperI/O Module (Continued) 4.4.2.2 LDN 01h - System Wakeup Control Table 4-8 lists registers that are relevant to the configura- tion of System Wakeup Control (SWC). These registers are Index Type Configuration Register or Action 30h R/W Activate. When bit ...
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SuperI/O Module (Continued) 4.4.2.3 LDN 02h - Infrared Communication Port Table 4-9 lists the configuration registers which affect the Infrared Communication Port (IRCP). Only the last register Index Type Configuration Register or Action 30h R/W Activate. See also bit 0 ...
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SuperI/O Module (Continued) 4.4.2.4 LDN 05h and 06h - ACCESS.bus Ports 1 and 2 ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identi- cal. Each ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. ACB1 ...
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SuperI/O Module (Continued) 4.4.2.5 LDN 08h - SP Configuration Table 4-13 lists the configuration registers which affect the Serial Port (SP). Only the last register (F0h) is described Index Type Configuration Register or Action 30h R/W Activate. See also bit ...
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SuperI/O Module (Continued) 4.5 REAL-TIME CLOCK (RTC) The RTC provides timekeeping and calendar management capabilities. The RTC uses a 32.768 KHz signal as the basic clock for timekeeping. It also includes 242 bytes of battery-backed RAM for general-purpose use. The ...
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SuperI/O Module (Continued) External Elements Choose C and C capacitors (see Figure 4-5 on page 80 match the crystal’s load capacitance. The load capaci- tance C “seen” by crystal Y is comprised with C ...
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SuperI/O Module (Continued) 4.5.3.1 Timekeeping Data Format Time is kept in BCD (Binary Coded Decimal) or binary for- mat, as determined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24-hour format, as determined by ...
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SuperI/O Module (Continued) 4.5.3.3 Power Supply The device is supplied from two supply voltages, as shown in Figure 4-8: • System standby power supply voltage, V • Backup voltage, from low capacity Lithium battery A standby voltage from ...
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SuperI/O Module (Continued) 4.5.3.4 System Power States The system power state may be No Power, Power On, Power Off, or Power Failure. Table 4-16 indicates the power-source combinations for each state. No other power- source combinations are valid. In addition, ...
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SuperI/O Module (Continued) 4.5.3.6 Interrupt Handling The RTC has a single Interrupt Request line which handles the following three interrupt conditions: • Periodic interrupt • Alarm interrupt • Update end interrupt The interrupts are generated if the respective enable bits ...
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SuperI/O Module (Continued) 4.5.4 RTC Registers The RTC registers can be accessed (see Section 4.4.2.1 "LDN 00h - Real-Time Clock" on page 74) at any time dur- ing normal operation mode (i.e.,when V ommended operation range). This access is disabled ...
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SuperI/O Module (Continued) Bit Description Index 00h Width: Byte 7:0 Seconds Data. Values may BCD format binary format. Index 01h Width: Byte 7:0 Seconds Alarm Data. Values may be 00 ...
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SuperI/O Module (Continued) Bit Description Index 0Bh Width: Byte 7 Set Mode. This bit is reset Timing updates occur normally. 1: User copy of time is “frozen”, allowing the time registers to be accessed whether or not ...
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SuperI/O Module (Continued) Bit Description Index 0Dh Width: Byte 7 Valid RAM and Time. This bit senses the voltage that feeds the RTC (VSB or VBAT) and indicates whether or not it was too low since the last time this ...
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SuperI/O Module (Continued) Parameter Seconds Minutes Hours 12-hour mode: 24-hour mode: Day (Sunday = 01) Date Month (January = 01) Year Century ...
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SuperI/O Module (Continued) 4.5.4.1 Usage Hints 1) Read bit 7 of CRD at each system power-up to vali- date the contents of the RTC registers and the CMOS RAM. When this bit is 0, the contents of these regis- ters ...
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SuperI/O Module (Continued) 4.6 SYSTEM WAKEUP CONTROL (SWC) The SWC wakes up the system by sending a power-up request to the ACPI controller in response to the following maskable system events: • Modem ring (RI#) • Programmable Consumer Electronics IR ...
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SuperI/O Module (Continued) 4.6.2 SWC Registers The SWC registers are organized in two banks. The offsets are related to a base address that is determined by the SWC Base Address Register in the logical device configu- ration. The lower three ...
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SuperI/O Module (Continued) Table 4-27. Banks 0 and 1 - Common Control and Status Registers Bit Description Offset 00h Width: Byte This register is set to 00h on power- Management Events" on page 136.) 7 Reserved. 6 Reserved. ...
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SuperI/O Module (Continued) Table 4-28. Bank 1 - CEIR Wakeup Configuration and Control Registers Bit Description Bank 1, Offset 03h Width: Byte This register is set to 00h on power- 7:6 Reserved. 5:4 CEIR Protocol Select. 00: RC5 ...
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SuperI/O Module (Continued) Table 4-28. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued) Bit Description These two registers (IRWTR1L and IRWTR1H) define the low and high limits of time range 1 (see Table 4-24 on page 92). The ...
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SuperI/O Module (Continued) 4.7 ACCESS.BUS INTERFACE The SC1100 has two ACCESS.bus (ACB) controllers. ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer, Intel's SMBus, and Phil- 2 ips’ The ACB can be configured as ...
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SuperI/O Module (Continued) 4.7.3 Acknowledge (ACK) Cycle The ACK cycle consists of two signals: the ACK clock pulse sent by the master with each byte transferred, and the ACK signal sent by the receiving device (see Figure 4- 15). The ...
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SuperI/O Module (Continued) 4.7.4 Acknowledge After Every Byte Rule According to this rule, the master generates an acknowl- edge clock pulse after each byte transfer, and the receiver sends an acknowledge signal after every byte received. There are two exceptions ...
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SuperI/O Module (Continued) Sending the Address Byte When the device is the active master of the ACCESS.bus (ACBST[1] is set), it can send the address on the bus. The address sent should not be the device’s own address, as defined ...
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SuperI/O Module (Continued) Master Error Detection The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer, or the acknowledge cycle) and a conflict on the data lines of the ACCESS.bus ...
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SuperI/O Module (Continued) 4.7.10 ACB Registers Each functional block is associated with a Logical Device Number (LDN) (see Section 4.3.2 "Banked Logical Device Registers" on page 68). ACCESS.Bus Port 1 is assigned Offset Type 00h R/W 01h R/W 02h R/W ...
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SuperI/O Module (Continued) Bit Description 2 NMATCH (New Match). (R/W1C) Writing 0 to this bit is ignored. If ACBCTL1[2] is set, an interrupt is sent when this bit is set. 0: Software writes 1 to this bit. 1: Address byte ...
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SuperI/O Module (Continued) Bit Description 4 ACK (Acknowledge). This bit is ignored in transmit mode. When the device acts as a receiver (slave or master), this bit holds the stop transmitting instruction that is transmitted during the next acknowledge cycle. ...
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SuperI/O Module (Continued) 4.8 LEGACY FUNCTIONAL BLOCKS This section briefly describes the following blocks that pro- vide legacy device functions: • Serial Port (SP), UART functionality. • Infrared Communication Port. Notes • The Serial Port is similar to SCC1 in ...
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SuperI/O Module (Continued Offset Type 00h R/W 01h R/W 02h --- 03h W R/W 04h-07h --- 1. When bit ...
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SuperI/O Module (Continued) Register Offset Name 7 00h RXD TXD 01h 1 IER RSVD 2 IER 02h 1 FEN[1:0] EIR RSVD 2 EIR FCR RXFTH[1:0] 03h 3 BKSE LCR 3 BKSE BSR 04h 1 MCR 2 MCR 05h LSR ER_INF ...
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SuperI/O Module (Continued) Register Offset Name 7 00h BGD(L) 01h BGD(H) 02h EXCR1 BTEST 03h LCR/BSR BKSE 04h EXCR2 LOCK 05h RSVD 06h TXFLV 07h RXFLV Register Offset Name 7 00h MRID 01h SH_LCR BKSE 02h SH_FCR RXFTH[1:0] 03h LCR/BSR ...
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SuperI/O Module (Continued) 4.8.2.2 IRCP Register and Bit Maps The tables in this subsection provide register and bit maps for Banks 0 through 7. Offset Type 00h RO W 01h R/W 02h RO W 03h W R/W 04h R/W 05h ...
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SuperI/O Module (Continued) Offset Type 00h R/W 01h R/W 02h --- 03h W R/W 04h-07h --- 1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-41. Offset ...
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SuperI/O Module (Continued) Offset Type 00h R/W 01h R/W 02h R/W 03h R/W 04h R/W RO 05h R/W RO 06h R/W RO 07h R/W RO Offset Type 00h R/W 01h R/W 02h R/W 03h R/W 04h R/W 05h RO 06h ...
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SuperI/O Module (Continued) Offset Type 00h R/W 01h R/W 02h R/W 03h R/W 04h R/W 05h-06h --- 07h R/W Register Offset Name 7 00h RXD TXD 01h 1 IER TMR_IE 2 IER 02h FEN[1:0] 1 EIR TMR_EV 2 EIR FCR ...
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SuperI/O Module (Continued) Register Offset Name 7 00h LBGD(L) 01h LBGD(H) 02h RSVD 03h LCR BKSE BSR BKSE 04h-07h RSVD Register Offset Name 7 00h BGD(L) 01h BGD(H) 02h EXCR1 BTEST 03h BSR BKSE 04h EXCR2 LOCK 05h RSVD 06h ...
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SuperI/O Module (Continued) Register Offset Name 7 00h TMR(L) 01h TMR(H) 02h IRCR1 03h BSR BKSE 04h TFRL(L)/ TFRCC(L) 05h TFRL(H)/ TFRCC(H) 06h RFRML(L)/ RFRCC(L) 07h RFRML(H)/ RFRCC(H) Register Offset Name 7 00h SPR2 01h SPR3 02h RSVD 03h BSR ...
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SuperI/O Module (Continued) Register Offset Name 7 00h IRRXDC 01h IRTXMC 02h RCCFG R_LEN 03h BSR BKSE 04h IRCFG1 STRV_MS 05h-06h RSVD 07h IRCFG4 RSVD Revision 1.1 Table 4-56. Bank 7 Bit Map Bits DBW[2:0] MCPW[2:0] T_OV ...
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Core Logic Module The Core Logic module is an enhanced PCI-to-Sub-ISA bridge (South Bridge), this module is ACPI-compliant, and provides AT/Sub-ISA functionality. The Core Logic module also contains state-of-the-art power management. Two bus mastering IDE controllers are included for ...
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Core Logic Module (Continued) 5.2 MODULE ARCHITECTURE AND CONFIGURATION The Core Logic architecture provides the internal functional blocks shown in Figure 5-1. • Fast-PCI interface to external PCI bus • IDE controllers (UDMA-33) • USB controllers • Sub-ISA bus interface ...
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Core Logic Module (Continued) 5.2.1 Fast-PCI Interface to External PCI Bus The Core Logic module provides a PCI bus interface that is both a slave for PCI cycles initiated by the GX1 module or other PCI master devices, and a ...
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Core Logic Module (Continued) 5.2.3 IDE Controller The Core Logic module integrates a PCI bus mastering, ATA-4 compatible IDE controller. This controller supports UltraDMA, Multiword DMA and Programmed I/O (PIO) modes. Two devices are supported on the IDE controller. The ...
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Core Logic Module (Continued) Physical Region Descriptor Table Address Before the controller starts a master transfer it is given a pointer to a Physical Region Descriptor Table. This pointer sets the starting memory location of the Physical Region Descriptors (PRDs). ...
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Core Logic Module (Continued) 5.2.3.4 UltraDMA/33 Mode The IDE controller of the Core Logic module supports UltraDMA/33. It utilizes the standard IDE Bus Master func- tionality to interface, initiate, and control the transfer.The UltraDMA/33 definition also incorporates a Cyclic Redun- ...
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Core Logic Module (Continued) 5.2.4 Universal Serial Bus The Core Logic module provides three complete, indepen- dent USB ports. Each port has a Data "Negative" and a Data "Positive" signal. The USB ports are Open Host Controller Interface (Open- HCI) ...
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Core Logic Module (Continued) 5.2.5.1 Sub-ISA Bus Cycles The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write results in two 16-bit ISA transactions or four ...
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Core Logic Module (Continued) REQ# GNT# FRAME# Fast-PCI IRDY# TRDY# STOP# BALE ISA RD#, IOR GX1 transaction 2 - IDE bus master - starts and completes 3 - End of ISA cycle Figure 5-3. PCI to ISA Cycles ...
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Core Logic Module (Continued) 5.2.5.5 ISA DMA DMA transfers occur between ISA I/O peripherals and sys- tem memory (i.e., not available externally). The data width can be either bits. Out of the seven DMA channels available, four ...
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Core Logic Module (Continued) 5.2.5.6 ROM Interface The Core Logic module positively decodes memory addresses 000F0000h-000FFFFFh FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory cycles cause the Core Logic module to claim the cycle, and generate an ISA bus memory cycle ...
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Core Logic Module (Continued) PCI FRAME# TRDY#, IRDY# GNT[x] ROMCS#, DOCCS#, F5BAR4CS#, F5BAR5CS#, IOCS0#, IOCS1# PAR, DEVSEL#, STOP# AD[31:0], C/BE[3:0]# Figure 5-6. PCI Change to Sub-ISA and Back 5.2.6 AT Compatibility Logic The Core Logic module integrates: • Two 8237-equivalent ...
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Core Logic Module (Continued) In block transfer mode, the DMA controller executes all of its transfers consecutively without releasing the PCI bus. In demand transfer mode, DMA transfer cycles continue to occur as long as DRQ is high or terminal ...
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Core Logic Module (Continued) DMA Page Registers and Extended Addressing The DMA Page registers provide the upper address bits during DMA cycles. DMA addresses do not increment or decrement across page boundaries. Page boundaries for the 8-bit channels (Channels 0 ...
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Core Logic Module (Continued) 5.2.6.3 Programmable Interrupt Controller The Core Logic module contains two 8259A-equivalent programmable interrupt controllers, with eight interrupt request lines each, for a total of 16 interrupts. The two con- trollers are cascaded internally, and two of ...
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Core Logic Module (Continued) PIC Interrupt Sequence A typical AT-compatible interrupt sequence is as follows. Any unmasked interrupt generates the internal INTR signal to the CPU. The interrupt controller then responds to the interrupt acknowledge (INTA) cycles from the CPU. ...
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Core Logic Module (Continued) 5.2.7 I/O Ports 092h and 061h System Control The Core Logic module supports control functions of I/O Ports 092h (Port A) and 061h (Port B) for PS/2 compatibil- ity. I/O Port 092h allows a fast assertion ...
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Core Logic Module (Continued) 5.2.8 Keyboard Support The Core Logic module can actively decode the keyboard controller I/O Ports 060h, 062h, 064h and 066h, and gener- ate an LPC bus cycle. Keyboard positive decoding can be disabled if F0 Index ...
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Core Logic Module (Continued) 5.2.9 Power Management Logic The Core Logic module integrates advanced power man- agement features including idle timers for common system peripherals, address trap registers for programmable address ranges for I/O or memory accesses, four program- mable ...
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Core Logic Module (Continued) SL1 Sleep State (ACPI S1) In this state the core processor Suspend mode (all its clocks are stopped, including the memory controller). The SDRAM is placed in self-refresh mode. All other SC1100 and ...
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Core Logic Module (Continued) 5.2.9.3 Power Planes Control The SC1100 supports up to three power planes. Three sig- nals are used to control these power planes. Table 5-6 describes the signals and when each is asserted. Table 5-6. Power Planes ...
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Core Logic Module (Continued) Power Button The power button (PWRBTN#, ball AF15) input provides two events: a wake request, and a sleep request. For both these events, the PWRBTN# signal is debounced (i.e., the signal state is transferred only after ...
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Core Logic Module (Continued) 5.2.10.1 APM Support Many notebook computers rely solely on an Advanced Power Management (APM) driver for enabling the operat- ing system to power-manage the CPU. APM provides sev- eral services which enhance management; but in its ...
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Core Logic Module (Continued) SMI Speedup Disable: If the Suspend Modulation feature is being used for CPU power management, the occurrence of an SMI disables Suspend Modulation so that the system operates at full speed while in SMM. There are ...
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Core Logic Module (Continued) General Purpose Timers The Core Logic module contains two general purpose idle timers, General Purpose Timer 1 (F0 Index 88h) and Gen- eral Purpose Timer 2 (F0 Index 8Ah). These two timers are similar to the ...
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Core Logic Module (Continued) SMI# Asserted If Bit (External SMI) GX1 Module Core Logic F1BAR0+I/O Module Offset 02h Read to Clear to determine top-level source of SMI Bits [15:10] Other_SMI Bit 9 GTMR_TRP_SMI Bits [8:0] Other_SMI Top ...
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Core Logic Module (Continued) 5.2.10.4 Power Management Programming Summary Table 5-9 provides a programming register summary for the power management timers, traps, and functions. For com- Table 5-9. Device Power Management Programming Summary Device Power Management Resource Traps Idle Timers ...
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Core Logic Module (Continued) 5.2.11 GPIO Interface GPIOs in the Core Logic module are provided for system control. For further information, see Section 3.2 "Multiplexing, Interrupt Selection, and Base Address Regis- ters" on page 50 and Table ...
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Core Logic Module (Continued) Physical Region Descriptor Table Address Before the bus master starts a master transfer it must be pro- grammed with a pointer (PRD Table Address register Physical Region Descriptor Table. This pointer sets the start- ...
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Core Logic Module (Continued) 4) Read the SMI Status register to clear the Bus Master Error and End of Page bits (bits 1 and 0). Set the correct direction to the Read or Write Control bit (Command register bit 3). ...
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Core Logic Module (Continued) 5.2.12.2 AC97 Codec Interface The AC97 codec (e.g., LM4548) is the master of the serial interface and generates the clocks to Core Logic module. Figure 5-13 shows the signal connections between a codec and the SC1100: ...
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Core Logic Module (Continued) 5.2.12.3 VSA Technology Support Hardware The Core Logic module incorporates the required hard- ware in order to support the Virtual System Architecture (VSA™) technology for capture and playback of audio using an external codec. This eliminates ...
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Core Logic Module (Continued) Fast Path Write captures the data and address bit 1 (A1) of the first access, but does not generate an SMI stored in F3BAR0+Memory Offset 14h[15]. The second access causes an SMI, and the ...
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Core Logic Module (Continued) 5.2.12.4 IRQ Configuration Registers The Core Logic module provides the ability to set and clear IRQs internally through software control. If the IRQs are configured for software control, they do not respond to external hardware. There ...
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Core Logic Module (Continued) 5.2.13.1 LPC Interface Signal Definitions The LPC specification lists seven required and six optional signals for supporting the LPC interface. Many of the sig- nals are the same signals found on the PCI interface and do ...
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Core Logic Module (Continued) 5.3 REGISTER DESCRIPTIONS The Core Logic module is a multi-function module. Its reg- ister space can be broadly divided into three categories in which specific types of registers are located: 1) Chipset Register Space (F0-F3, F5; ...
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Core Logic Module (Continued) 5.3.2 Register Summary The tables in this subsection summarize the registers of the Core Logic module. Included in the tables are the register’s reset values and page references where the bit formats are found. Note: Function ...
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Core Logic Module (Continued) Table 5-14. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support Summary (Continued) Width F0 Index (Bits) Type Name 70h-71h 16 R/W IOCS1# Base Address Register 72h 8 R/W IOCS1# Control Register 73h ...
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Core Logic Module (Continued) Table 5-14. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support Summary (Continued) Width F0 Index (Bits) Type Name C0h-C3h 32 R/W User Defined Device 1 Base Address Register C4h-C7h 32 R/W User ...
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Core Logic Module (Continued) Table 5-15. F0BAR0: GPIO Support Registers Summary F0BAR0+ Width I/O Offset (Bits) Type Name 00h-03h 32 R/W GPDO0 — GPIO Data Out 0 Register 04h-07h 32 RO GPDI0 — GPIO Data In 0 Register 08h-0Bh 32 ...
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Core Logic Module (Continued) Table 5-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary Width F1 Index (Bits) Type Name 00h-01h 16 RO Vendor Identification Register 02h-03h 16 RO Device Identification Register 04h-05h 16 R/W PCI Command ...
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Core Logic Module (Continued) Table 5-19. F1BAR1: ACPI Support Registers Summary F1BAR1+ Width I/O Offset (Bits) Type Name 00h-03h 32 R/W P_CNT — Processor Control Register 04h 8 RO Reserved, do not read 05h 8 RO P_LVL3 — Enter C3 ...
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Core Logic Module (Continued) Table 5-20. F2: PCI Header Registers for IDE Controller Support Summary Width F2 Index (Bits) Type Name 00h-01h 16 RO Vendor Identification Register 02h-03h 16 RO Device Identification Register 04h-05h 16 R/W PCI Command Register 06h-07h ...
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Core Logic Module (Continued) Table 5-22. F3: PCI Header Registers for XpressAUDIO Support Summary Width F3 Index (Bits) Type Name 00h-01h 16 RO Vendor Identification Register 02h-03h 16 RO Device Identification Register 04h-05h 16 R/W PCI Command Register 06h-07h 16 ...
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Core Logic Module (Continued) Table 5-23. F3BAR0: XpressAUDIO Support Registers Summary (Continued) F3BAR0+ Memory Width Offset (Bits) Type Name 3Ch-3Fh 32 R/W Audio Bus Master 3 PRD Table Address 40h 8 R/W Audio Bus Master 4 Command Register 41h 8 ...
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Core Logic Module (Continued) Table 5-24. F5: PCI Header Registers for X-Bus Expansion Support Summary Width F5 Index (Bits) Type Name 00h-01h 16 RO Vendor Identification Register 02h-03h 16 RO Device Identification Register 04h-05h 16 R/W PCI Command Register 06h-07h ...
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Core Logic Module (Continued) Table 5-26. PCIUSB: USB PCI Configuration Register Summary PCIUSB Width Index (Bits) Type Name 00h-01h 16 RO Vendor Identification 02h-03h 16 RO Device Identification 04h-05h 16 R/W Command Register 06h-07h 16 R/W Status Register 08h 8 ...
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Core Logic Module (Continued) Table 5-27. USB_BAR: USB Controller Registers Summary USB_BAR0 +Memory Width Offset (Bits) Type Name 00h-03h 32 R/W HcRevision 04h-07h 32 R/W HcControl 08h-0Bh 32 R/W HcCommandStatus 0Ch-0Fh 32 R/W HcInterruptStatus 10h-13h 32 R/W HcInterruptEnable 14h-17h 32 ...
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Core Logic Module (Continued) Table 5-28. ISA Legacy I/O Register Summary I/O Port Type Name DMA Channel Control Registers (Table 5-43) 000h R/W DMA Channel 0 Address Register 001h R/W DMA Channel 0 Transfer Count Register 002h R/W DMA Channel ...
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Core Logic Module (Continued) Table 5-28. ISA Legacy I/O Register Summary (Continued) I/O Port Type Name 489h R/W DMA Channel 6 High Page Register 48Ah R/W DMA Channel 7 High Page Register 48Bh R/W DMA Channel 5 High Page Register ...
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Core Logic Module (Continued) 5.4 CHIPSET REGISTER SPACE The Chipset Register Space of the Core Logic module is comprised of five separate functions (F0-F3 and F5, note that F4 is reserved), each with its own register space. Base Address Registers ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 3 Special Cycles. Allow the Core Logic module to respond to special cycles. 0: Disable. 1: Enable. (Default) This ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 0Ch 7:0 PCI Cache Line Size Register. This register sets the size of the PCI cache line, in ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 40h 7:6 Reserved. Must be set Reserved. Must be set Reserved. Must ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 43h 7:5 Reserved. Must be set Enable PCI Delayed Transactions for Access to I/O Address ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 46h 7:6 Reserved. Resets to 11 (PCI Function 5). When asserted (set to 1), enables the ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 2:0 ISA Clock Divisor. Determines the divisor of the PCI clock used to make the ISA clock, which is ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 0 Lower ROM Size. Selects lower ROM addressing size in which ROMCS# goes active. 0: Lower ROM access are ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 1 Keyboard Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O Ports 060h and 064h ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 3:0 INTA# (Ball AD26) Target Interrupt. 0000: Disable 0001: IRQ1 0010: Reserved 0011: IRQ3 Index 5Dh Indicates target interrupts ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 6Eh-6Fh 15:8 Reserved. Must be set to FFh. 7:4 ROM Size Index 52h[ 0000: ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 4:0 IOCS0# I/O Address Range. This 5-bit field is used to select the range of IOCS0#. 00000: 1 Byte ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 1 Idle Timers. Device idle timers. 0: Disable. 1: Enable. Note: Disable at this level does not reload the ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 2 Parallel/Serial Idle Timer Enable. Turn on Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch) and generate an ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 3 Keyboard/Mouse Access Trap. 0: Disable. 1: Enable. If this bit is enabled and an access occurs in the ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 5 ACPI Timer SMI. Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 85h Second Level PME/SMI Status Mirror Register 2 (RO) The bits in this register contain second level status ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 4 Secondary Hard Disk Idle Timer SMI Status. Indicates whether or not an SMI was caused by expiration of ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 2 Codec SDATA_IN SMI Status. Indicates whether or not an SMI was caused by AC97 codec producing a positive ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 2 Re-trigger General Purpose Timer 1 on Parallel/Serial Port Activity. 0: Disable. 1: Enable. Any access to the parallel ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 2 Re-trigger Timer on GPIO7 Pin Transition. A rising-edge transition on the GPIO7 pin reloads GP Timer 2 (F0 ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 7:0 Suspend Signal Deasserted Counter. This 8-bit counter represents the number of 32 µs intervals that the internal SUSP# ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 9Ch-9Dh 15:0 Parallel / Serial Idle Timer Count. This idle timer is used to determine when the parallel ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index AEh 7:0 Software CPU Suspend Command. If bit 0 in the Clock Stop Control register is set low ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index B9h 7:0 PIC Shadow. This 8-bit port sequences through the following list of shadowed Interrupt Controller registers. At ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Note: This register configures the Core Logic module to support a 3V Suspend mode. Setting bit 0 causes the ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 6:0 Mask. If bit (I/O): Bit 6 0: Disable write cycle tracking. 1: Enable write cycle ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 1 GPWIO1 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO1 pin. ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 0 Hard Disk Idle Timer SMI Status. Indicates whether or not an SMI was caused by expiration of Hard ...
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Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index F7h The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O ...
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Core Logic Module (Continued) 5.4.1.1 GPIO Support Registers F0 Index 10h, Base Address Register 0 (F0BAR0) points to the base address of where the GPIO runtime and configu- Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers Bit Description Offset 00h-03h 31:0 ...
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Core Logic Module (Continued) Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued) Bit Description Offset 10h-13h 31:0 GPIO Data Out. Bits [31:0] of this register correspond to GPIO63-GPIO32 signals, respectively. The value of each bit deter- mines the value driven ...
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Core Logic Module (Continued) Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued) Bit Description 4:0 Signal Select. Selects the GPIO signal to be configured in the Bank selected via bit 5 setting (i.e., Bank 0 or Bank 1). See Table ...
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Core Logic Module (Continued) Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued) Bit Description 3 Lock. This bit locks the selected GPIO signal. Once this bit is set software, it can only be cleared ...
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Core Logic Module (Continued) 5.4.1.2 LPC Support Registers F0 Index 14h, Base Address Register 1 (F0BAR1) points to the base address of the register space that contains the configuration registers for LPC support. Table 5-31 gives the bit formats of ...