CY23FS04ZC Cypress Semiconductor Corporation., CY23FS04ZC Datasheet
CY23FS04ZC
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CY23FS04ZC Summary of contents
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Features • Internal DCXO for continuous glitch-free operation • Zero input-output propagation delay • Low-jitter (< RMS) outputs • Low Output-to-Output skew (< 200 ps) • 4.17 MHz–170 MHz reference input • Supports industry standard input crystals • ...
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Pin Definition Pin Number Pin Name 1,2 REF[1:2] Reference clock inputs. 5V-tolerant 3,4 CLKB[1:2] Bank B clock outputs. 14,13 CLKA[1:2] Bank A clock outputs. 15 FBK Feedback input to the PLL. 12,5 S[1:2] Frequency select pins and PLL and DCXO ...
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Table 2. FailSafe Timing Table Parameter Description t Fail#/Safe Assert Delay FSL t Fail#/Safe De-assert Delay FSH In this mode, should the reference ...
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Failsafe typical frequency settling time Initial valid Ref1=20MHz +100ppm, 150 100 Figure 4. FailSafe Reference Switching Behavior Figure 5. FailSafe Effective Loop Bandwidth (min) Document #: 38-07304 Rev. *C then switching to REF2=20MHz 0.45 1.3 SETTLING TIME ...
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Figure 6. Sample Timing of Muxing Between Two Reference Clocks 180°C Out of Phase and Resulting ...
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XTAL Selection Criteria and Application Example Choosing the appropriate XTAL will ensure the FailSafe device will be able to span an appropriate frequency of operation. Also, the XTAL parameters will determine the holdover frequency stability. Critical parameters are as follows. ...
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Figure 8. Frequency vs. Cload Behavior for Example XTAL Table 3. Pullability Range fro XTAL with ...
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Absolute Maximum Conditions Parameter Description V Supply Voltage DD V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J ESD ESD Protection (Human Body Model) HBM Ø Dissipation, Junction to Case JC Ø ...
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... Dynamic Phase Offset D( φ Cycle-to-cycle Jitter J(CC) Ordering Information Part Number CY23FS04ZI CY23FS04ZIT CY23FS04ZC CY23FS04ZCT Lead-free CY23FS04ZXI CY23FS04ZXIT CY23FS04ZXC CY23FS04ZXCT Notes The reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as ( φ Parameters guaranteed by design and characterization, not 100% tested in production. ...
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Package Drawing and Dimensions 1 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.05[0.002] 0.85[0.033] 0.15[0.006] 0.95[0.037] 4.90[0.193] 5.10[0.200] FailSafe is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trade- marks of their ...
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Document History Page Document Title: CY23FS04 Failsafe™ 2.5V/ 3.3V Zero Delay Buffer Document #: 38-07304 Rev. *C Orig. of REV. ECN NO. Issue Date Change ** 123698 04/24/03 *A 223811 See ECN RGL/ZJX Changed the XTAL Specifications table. *B 276712 ...