CY24207ZC-1 Cypress Semiconductor Corporation., CY24207ZC-1 Datasheet

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CY24207ZC-1

Manufacturer Part Number
CY24207ZC-1
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY24207ZC-1
Manufacturer:
CY
Quantity:
75
Cypress Semiconductor Corporation
Document #: 38-07553 Rev. *A
Features
Frequency Select Options
Block Diagram
Note:
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with Analog Adjust
• 3.3V operation
Part Number
XOUT
VCXO
1.
OE
CY24207-1
CY24207-2
XIN
0
0
0
0
1
1
1
1
FS1
FS0
OE
“off” = output is driven high.
FS1
0
0
1
1
0
0
1
1
OSC.
FS0
Outputs
0
1
0
1
0
1
0
1
4
4
Q
67.357642 (3.8 ppm)
53.946053 (–1 ppm)
CLK1/CLK2 (-1)
VDDL
P
27-MHz Crystal Input
27-MHz Crystal Input
67.425
Input Frequency
off
off
off
off
54
VCO
PLL
VDD
AVDD
[1]
3901 North First Street
AVSS
MULTIPLEXER
VSS
DIVIDERS
OUTPUT
68.400599(–8.8 ppm)
AND
53.946053 (–1 ppm)
CLK1/CLK2 (-2)
VSSL
Two copies of 27-MHz reference clock output, two copies of
54/53.946053/67.425/67.357642 MHz (frequency selectable)
Two copies of 27-MHz reference clock output, two copies of
54/53.946053/67.425/68.400599 MHz (frequency selectable)
Benefits
67.425
• Internal PLL with up to 400-MHz internal operation
• Meets critical timing requirements in complex system
• Large ±200-ppm range, better linearity
• Enables application compatibility
off
off
off
off
54
designs
[1]
CLK1
REFCLK1
CLK2
REFCLK2
San Jose
Output Frequency Range
PDP Clock Generator
REFCLK 1/2
,
CA 95134
27
27
27
27
27
27
27
27
REFCLK2
REFCLK1
Pin Configuration
VCXO
AVDD
AVSS
MediaClock™
VSSL
VDD
XIN
16-pin TSSOP
Revised July 31, 2003
1
2
3
4
5
6
7
8
408-943-2600
CY24207
16
15
14
13
12
11
10
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
9
CLK1
FS1
FS0
CLK2
OE
VSS
VDDL
XOUT
[+] Feedback

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CY24207ZC-1 Summary of contents

Page 1

Features • Integrated phase-locked loop (PLL) • Low-jitter, high-accuracy outputs • VCXO with Analog Adjust • 3.3V operation Part Number Outputs Input Frequency CY24207-1 4 27-MHz Crystal Input CY24207-2 4 27-MHz Crystal Input Block Diagram XIN Q OSC. VCO XOUT ...

Page 2

Pin Description Pin No. Name 1 XIN Reference crystal input 2 V Voltage supply Analog voltage supply DD 4 VCXO Input analog control for VCXO 5 AV Analog ground CLK ground SSL 7 REFCLK2 ...

Page 3

Absolute Maximum Conditions Supply Voltage ( )..................–0.5 to +7.0V DD DDL DDL DC Input Voltage........................................ –0. Storage Temperature (Non-condensing).....– +125 C Junction Temperature ................................ – +125 C Pullable Crystal Specifications ...

Page 4

AC Electrical Specifications [2] Parameter Name DC Output Duty Cycle ER Rising Edge Rate EF Falling Edge Rate t Clock Jitter 9 t PLL Lock Time 10 Test and Measurement Set-up V DDs 0.1 F Voltage and Timing Definitions Clock ...

Page 5

... Ordering Information Ordering Code CY24207ZC-1 16-pin TSSOP CY24207ZC-1T 16-pin TSSOP CY24207ZC-2 16-pin TSSOP CY24207ZC-2T 16-pin TSSOP Package Drawing and Dimensions 16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-07553 Rev ...

Page 6

Document History Page Document Title: CY24207 MediaClock™ PDP Clock Generator Document Number: 38-07553 REV. ECN NO. Issue Date *.* 127230 06/26/03 *A 128248 07/31/03 Document #: 38-07553 Rev. *A Orig. of Change Description of Change RGL New Data Sheet IJATMP ...

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