CY2509 Cypress Semiconductor Corporation., CY2509 Datasheet

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CY2509

Manufacturer Part Number
CY2509
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07230 Rev. *C
Features
• Spread Aware™—designed to work with SSFTG
• Well suited to both 100- and 133-MHz designs
• Ten (CY2509) or eleven (CY2510) LVCMOS/LVTTL
• 50 ps typical peak cycle-to-cycle jitter
• Single output enable pin for CY2510 version, dual pins
• 3.3V power supply
• On board 25Ω damping resistors
• Available in 24-pin TSSOP package
• Improved tracking skew, but narrower frequency
Block Diagram
OE0:4
OE5:8
reference signals
outputs
on CY2509 devices allow shutting down a portion of the
outputs
support limit when compared to W132-09B/10B
OE
Configuration of these blocks dependent upon specific option being used
CLK
FBIN
Spread Aware™, Ten/Eleven Output Zero Delay Buffer
PLL
3901 North First Street
Q9
Q0
Q1
Q2
Q3
Q5
Q6
Q7
Q8
Q4
FBOUT
Key Specifications
Operating Voltage: ................................................3.3V±10%
Operating Range: ....................... 40 MHz < f
Cycle-to-Cycle Jitter: ................................................ <100 ps
Output to Output Skew: ........................................... <100 ps
Phase Error Jitter:..................................................... <100 ps
Pin Configurations
FBOUT
FBOUT
AGND
OE0:4
AGND
GND
GND
GND
GND
VDD
VDD
VDD
VDD
OE
Q0
Q1
Q2
Q3
Q4
Q0
Q1
Q2
Q3
Q4
San Jose
10
12
11
10
12
11
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
,
CA 95134
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
Revised July 01, 2005
CLK
AVDD
VDD
Q8
Q7
GND
GND
Q6
Q5
VDD
OE5:8
FBIN
CLK
AVDD
VDD
Q9
Q8
GND
GND
Q7
Q6
Q5
VDD
FBIN
CY2509/10
OUT
408-943-2600
< 140 MHz
[+] Feedback

Related parts for CY2509

CY2509 Summary of contents

Page 1

... Ten (CY2509) or eleven (CY2510) LVCMOS/LVTTL outputs • typical peak cycle-to-cycle jitter • Single output enable pin for CY2510 version, dual pins on CY2509 devices allow shutting down a portion of the outputs • 3.3V power supply • On board 25Ω damping resistors • Available in 24-pin TSSOP package • ...

Page 2

... GND (LOW, 0) outputs Q5:8 are disabled to a LOW state. enough to meet all the requirements of the memory and logic on the DIMM. The CY2509/10 takes in the signal from the motherboard and buffers out clock signals with enough drive to support all the DIMM board clocking needs. The CY2509/10 is also designed to meet the needs of new PC133 SDRAM designs, operating to 133 MHz ...

Page 3

... Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs form the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for. Reference Signal Feedback Input Figure 2. Six Output Buffers in the Feedback Path CY2509/10 3.3V FB 0.1 µF 10 µF 10 µF FB VDD V DD 0.1 µ ...

Page 4

... DD = 0°C to +70° 3.3V ±10 Test Condition [5] 30-pF load 0.8V to 2.0V, 30-pF load 2.0V to 0.8V, 30-pF load [3, 4] Measured All outputs loaded equally 30-pF load Power supply stable CY2509/10 Rating Unit –0.5 to +7.0 V –65 to +150 ° +70 °C –55 to +125 °C 0.5 W Min. Typ. Max. Unit – ...

Page 5

... Package Type Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial PIN 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 24 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] 0.05[0.002] SEATING 0.15[0.006] PLANE CY2509/10 Temperature Range 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85119-*A Page [+] Feedback ...

Page 6

... Document History Page Document Title: CY2509/10 Spread Aware™, Ten/Eleven Output Zero Delay Buffer Document Number: 38-07230 Issue REV. ECN NO. Date ** 110495 01/07/02 *A 122844 12/14/02 *B 352015 See ECN *C 385383 See ECN Document #: 38-07230 Rev. *C Orig. of Change Description of Change SZV Change from Spec number: 38-00914 to 38-07230 ...

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