CY28341ZC-2 Cypress Semiconductor Corporation., CY28341ZC-2 Datasheet
CY28341ZC-2
Related parts for CY28341ZC-2
CY28341ZC-2 Summary of contents
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Universal Clock Chip for VIA™P4M/KT/KM400 Features • Supports VIA P4M/KM/KT/266/333/400 chipsets ® • Supports Pentium 4, Athlon™ processors • Supports two DDR DIMMS • Supports three SDRAM DIMMS at 100 MHz • Provides: — two different programmable CPU clock pairs ...
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Pin Description Pin Number Pin Name 3 XIN 4 XOUT 1 FS0/REF0 VDDR 56 VTTPWRGD# VDDR REF1 VDDR 44,42,38, DDRT 36,32,30 (0:5)/SDRAM (0,2,4,6,8,10) VDDD 43,41,37 DDRC 35,31,29 (0:5)/SDRAM (1,3,5,7,9,11) VDDD 7 SELP4_K7 / AGP1 VDDAGP 12 MULTSEL/PCI2 VDDPCI 53 ...
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Pin Description (continued) Pin Number Pin Name 11 SELSDR_DDR#/ PCI1 VDDPCI 21 FS2/24_48M VDD48M 6 AGP0 VDDAGP 8 AGP2 VDDAGP 25 IREF 28 SDATA 27 SCLK 26 PD#/SRESET# 45 BUF_IN 46 FBOUT 5 VDDAGP 51 VDDC 16 VDDPCI 55 ...
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Power Management Functions All clocks can be individually enabled or stopped via the two-wire control interface. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stop and on transitions ...
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Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write 10 Acknowledge from slave 11:18 Command Code – 8-bit ‘1xxxxxxx’ stands for byte operationbit[6:0] of the command ...
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Byte 2: PCI Clock Register Bit @Pup Pin# Name 7 0 PCI_DRV PCI_F PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 ...
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Byte 5: SDR/DDR Clock Register Bit @Pup Pin# Name BUF_IN threshold voltage FBOUT 5 1 29,30 DDRT/C5/SDRAM(10 31,32 DDRT/C4/SDRAM(8, output enabled (running output disabled asynchronously in a ...
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Byte 7: Dial-a-Frequency Control Register N Bit @Pup Pin Reserved 6 0 N6, MSB N0, LSB Byte 8: Silicon Signature Register ...
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Spread Spectrum Clock Generation (SSCG) Spread Spectrum is enabled/disabled via SMBus register Byte 1, Bit 7. Table 9. Spread Spectrum Table Mode SST1 SST0 ...
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Power-down Deassertion (P4 Mode) The power-up latency needs to less than 3 mS ...
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Power-down Deassertion (K7 Mode): When deasserted PD# to high level, all clocks are enabled and start running on the rising edge of the next full period in order to guarantee a glitch-free operation, no partial clock pulses ...
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Figure 7. Clock Generator Power-up/Run State Diagram (with P4 processor SELP4_K7#=1) Connection Circuit DDRT/C Signals For open-drain CPU output signals ...
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CPUT MULTSEL CPUT# R ref Table 11. Lumped Test Load Configuration Component tA1 tA2 49.9 LA1 LA2 T 3” PCB LB1 LB2 ...
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Maximum Ratings Input Voltage Relative to V :.............................. V SS Input Voltage Relative DDQ Storage Temperature: ................................– 150 C Operating Temperature: .................................... +70 C Maximum ESD .............................................................2000V Maximum Power ...
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AC Parameters (continued) Parameter Description T /T CPUT/C Rise and Fall Times R F Rise/Fall Matching T /T Rise/Fall Time Variation CPUCS_T/C to CPUT/C Clock Skew SKEW T CPUT/C Cycle to Cycle Jitter CCJ V Crossing Point ...
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AC Parameters (continued) Parameter Description T Any AGP to Any AGP Clock Skew SKEW T AGP(0:2) Cycle-to-Cycle Jitter CCJ PCI T PCI(_F,1:6) Duty Cycle DC T PCI(_F,1:6) Period PERIOD T PCI(_F,1:6) High Time HIGH T PCI(_F,1:6) Low Time LOW T ...
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... Shrunk Small Outline package (SSOP)–Tape and Reel CY28341ZC–2 56-pin Thin Shrunk Small Outline package(TSSOP) CY28341ZC–2T 56-pin Thin Shrunk Small Outline package(TSSOP)–Tape and Reel Package Drawing and Dimensions 56-pin Thin Shrunk Small Outline Package, Type mm) Z56 ...
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Document History Page Document Title: CY28341-2 Universal Clock Chip for VIA™P4M/KT/KM400 DDR Systems Document Number: 38-07471 REV. ECN NO. Issue Date ** 118589 09/18/02 *A 122938 12/19/02 *B 124914 04/23/03 *C 127161 06/10/03 Document #: 38-07471 Rev. *B Orig. of ...