CY28410ZC Cypress Semiconductor Corporation., CY28410ZC Datasheet

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CY28410ZC

Manufacturer Part Number
CY28410ZC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-07593 Rev. *C
Features
• Compliant with Intel
• Supports Intel P4 and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 96-MHz differential dot clock
• 48-MHz USB clocks
Block Diagram
VTT_PWRGD#
FS_[C:A]
SDATA
XOUT
SCLK
IREF
XIN
PD
PLL1
PLL2
Logic
XTAL
OSC
I
2
C
Network
Divider
£
CK410
PLL Ref Freq
Clock Generator for Intel
3901 North First Street
DOT96T
DOT96C
VDD_REF
REF
VDD_CPU
VDD_SRC
VDD_PCI
VDD_PCIF
VDD_48 MHz
USB_48
CPUT[0:1], CPUC[0:1],
CPU(T/C)2_ITP]
SRCT[1:6], SRCC[1:6]
PCI[0:5]
PCIF[0:2]
FS_B/TEST_MODE
VTT_PWRGD#/PD
• 33-MHz PCI clock
• Low-voltage frequency select input
• I
• Ideal Lexmark Spread Spectrum profile for maximum
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
PCIF0/ITP_EN
SRC4_SATAC
x2 / x3
SRC4-SATAT
electromagnetic interference (EMI) reduction
CPU
2
C support with readback capabilities
Pin Configuration
VDD_SRC
VDD_SRC
VDD_PCI
VDD_PCI
VSS_PCI
VSS_PCI
DOT96C
VDD_48
DOT96T
USB_48
VSS_48
SRCC1
SRCC2
SRCC3
SRCT1
SRCT2
SRCT3
PCIF1
PCIF2
FS_A
PCI3
PCI4
PCI5
x6 / x7
SRC
San Jose
£
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 SSOP/TSSOP
Grantsdale Chipset
PCI
,
x 9
CA 95134
REF
x 1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Revised Sept. 28, 2204
PCI2
PCI1
PCI0
FS_C/TEST_SEL
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
VDD_SRC
SRCT6
SRCC6
SRCT5
SRCC5
VSS_SRC
DOT96
x 1
408-943-2600
CY28410
USB_48
x 1

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CY28410ZC Summary of contents

Page 1

Clock Generator for Intel Features £ • Compliant with Intel CK410 • Supports Intel P4 and Tejas CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 96-MHz differential dot clock • 48-MHz USB ...

Page 2

Pin Definitions Pin No. Name 44,43,41,40 CPUT/C 36,35 CPUT2_ITP/SRCT7, CPUC2_ITP/SRCC7 14,15 DOT96T, DOT96C 18 FS_A 16 FS_B/TEST_MODE 53 FS_C/TEST_SEL 39 IREF 54,55,56,3,4,5 PCI 9,10 PCIF 8 PCIF0/ITP_EN 52 REF 46 SCLK 47 SDATA 26,27 SRC4_SATAT, SRC4_SATAC 19,20,22,23,2 SRCT/C 4,25,31,30,33, 32 ...

Page 3

Frequency Select Pins (FS_A, FS_B and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by ...

Page 4

Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description .... Data Byte /Slave Acknowledges .... Data Byte N –8 bits .... Acknowledge from slave .... Stop Table 4. Byte Read and Byte Write Protocol Byte ...

Page 5

Byte 1: Control Register 1 Bit @Pup DOT_96T USB_48 Reserved 2 1 CPU[T/C CPU[T/C CPUT/C SRCT/C Byte 2: Control Register 2 Bit @Pup ...

Page 6

Byte 3: Control Register 3 (continued) Bit @Pup Reserved Byte 4: Control Register 4 Bit @Pup 7 0 Reserved 6 0 DOT96[T/ Reserved 1 1 Reserved 0 1 ...

Page 7

Byte 6: Control Register 6 (continued) Bit @Pup 2 Externally CPUT/C selected 1 Externally CPUT/C selected 0 Externally CPUT/C selected Byte 7: Vendor ID Bit @Pup 7 0 Revision Code Bit Revision Code Bit ...

Page 8

Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with ...

Page 9

CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) PD (Power-down) Clarification The VTT_PWRGD# /PD pin ...

Page 10

PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD _A = 2.0V S0 ...

Page 11

Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC (Mil-Spec 883E ...

Page 12

AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V T ...

Page 13

AC Electrical Specifications Parameter Description V Voltage Low LOW V Crossing Point Voltage at 0.7V Swing OX V Maximum Overshoot Voltage OVS V Minimum Undershoot Voltage UDS V Ring Back Voltage RB SRC T SRCT and SRCC Duty Cycle DC ...

Page 14

AC Electrical Specifications Parameter Description T DOT96T and DOT96C Absolute PERIODAbs Period T DOT96T/C Cycle to Cycle Jitter CCJ L DOT96T/C Long Term Accuracy ACC DOT96T and DOT96C Rise and Fall R F Times T Rise/Fall Matching ...

Page 15

Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals. PCI/ USB REF For Differential CPU, SRC and DOT96 Output Signals The following ...

Page 16

... Ordering Information Part Number Standard CY28410OC 56-pin SSOP CY28410OCT 56-pin SSOP – Tape and Reel CY28410ZC 56-pin TSSOP CY28410ZCT 56-pin TSSOP – Tape and Reel Lead-free (Planned) CY28410OXC 56-pin SSOP CY28410OXCT 56-pin SSOP – Tape and Reel CY28410ZXC 56-pin TSSOP CY28410ZXCT 56-pin TSSOP – ...

Page 17

Package Drawing and Dimensions 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC 2 Purchase components from Cypress or one of its sublicensed ...

Page 18

Document History Page Document Title: CY28410 Clock Generator for Intel Document Number: 38-07593 REV. ECN NO. Issue Date ** 130204 12/24/03 *A 207740 See ECN *B 229399 See ECN *C 270664 See ECN Document #: 38-07593 Rev. *C £ Grantsdale ...

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