CY28435ZXC Cypress Semiconductor Corporation., CY28435ZXC Datasheet
CY28435ZXC
Related parts for CY28435ZXC
CY28435ZXC Summary of contents
Page 1
Clock Generator for Intel Features £ • Compliant to Intel CK410 • Supports Intel Prescott and Tejas CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 96-MHz differential dot clock • 48-MHz USB ...
Page 2
Pin Description Pin No. Name 1,7 VDD_PCI 2,6 VSS_PCI 3,55,56 DF/PCI I/O, SE 3.3V LVTTL input to enable Dynamic Frequency input/33-MHz clock output. 4 FS_E/PCI4 I/O,PU, 5 PCI 8 DF_EN/PCIF0 I/O, SE, 9 SRESET_EN/PCIF I/O, SE PCIF2 17 ...
Page 3
Pin Description (continued) Pin No. Name 53 FS_C/REF1 54 SRESET#/PCI0 Frequency Select Pins (FS_[A:E]) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C,FS_D and FS_E inputs prior to VTT_PWRGD# assertion (as seen by ...
Page 4
Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. ...
Page 5
Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description 18:11 Command Code – 8 bits 19 Acknowledge from slave 27:20 Data byte – 8 bits 28 Acknowledge from slave 29 Stop Control Registers Byte 0: ...
Page 6
Byte 2: Control Register 2 Bit @Pup Byte 3: Control Register 3 Bit @Pup 7 0 SRC[T/C SRC[T/C SRC[T/C]5 4 ...
Page 7
Byte 5: Control Register 5 Bit @Pup 7 0 SRC[T/ RESERVED 5 0 RESERVED 4 0 RESERVED 3 0 SRC[T/C][7: RESERVED 1 0 CPU[T/C CPU[T/C]0 Byte 6: Control Register 6 Bit @Pup 7 0 ...
Page 8
Byte 8: Control Register 8 Bit @Pup 7 0 CPU_SS 6 0 CPU_DWN_SS 5 0 SRC_SS_OFF 4 0 SRC_SS 3 0 RESERVED RESERVED Byte 9: Control Register 9 Bit @Pup 7 0 DF_Limit2 6 ...
Page 9
Byte 10: Control Register 10 (continued) Bit @Pup 0 0 WD_EN Byte 11: Control Register 11 Bit @Pup 7 0 CPU_DAF_N7 6 0 CPU_DAF_N6 5 0 CPU_DAF_N5 4 0 CPU_DAF_N4 3 0 CPU_DAF_N3 2 0 CPU_DAF_N2 1 0 CPU_DAF_N1 0 ...
Page 10
Byte 14: Control Register 14 (continued) Bit @Pup 4 0 SMSW_SEL 3 0 RESERVED 2 0 RESERVED Recovery_N8 Byte 15: Control Register 15 Bit @Pup 7 0 Recovery Recovery Recovery ...
Page 11
Table 4. Crystal Recommendations Frequency Cut Loading Load Cap (Fund) 14.31818 MHz AT Parallel Figure 2. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to ...
Page 12
Dynamic Frequency Dynamic Frequency – Dynamic Frequency (DF technique to increase the CPU frequency dynamically from any starting value. The user selects the starting point, either by HW, FSEL, or DAF then enables DF. After that, DF will ...
Page 13
It is not recommended to enable overclocking and change the N values of both PLLs in the same SMBUS block write. Watchdog Timer The Watchdog timer ...
Page 14
HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthe- sizer also an asynchronous input ...
Page 15
FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD_A = 2.0V S0 Power Off Figure 7. Clock Generator Power-up/Run State Diagram Document #: 38-07664 Rev. *B PRELIMINARY 0.2-0.3mS W ...
Page 16
Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
Page 17
AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V (SSC ...
Page 18
AC Electrical Specifications Parameter Description T CPUT/C Cycle to Cycle Jitter CCJ L Long Term accuracy ACC CPUT and CPUC Rise and Fall Times Rise/Fall Matching RFM Rise Time Variation 'T R Fall Time ...
Page 19
AC Electrical Specifications Parameter Description Edge Rate Falling edge rate T Any PCI clock to Any PCI clock Skew SKEW T PCIF and PCI Cycle to Cycle Jitter CCJ DOT T DOT96T and DOT96C Duty Cycle DC T DOT96T and ...
Page 20
AC Electrical Specifications Parameter Description Edge Rate Falling edge rate T REF Cycle to Cycle Jitter CCJ ENABLE/DISABLE and SET-UP T Clock Stabilization from Power-up STABLE Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows ...
Page 21
... Figure 11. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Lead-free CY28435OXC 56-pin SSOP CY28435OXCT 56-pin SSOP – Tape and Reel CY28435ZXC 56-pin TSSOP CY28435ZXCT 56-pin TSSOP – Tape and Reel Document #: 38-07664 Rev. *B PRELIMINARY : : : Figure 10. 0.7V Single-ended Load Configuration 3 ...
Page 22
... C Patent Rights to use these components defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. Dial-A-Frequency is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07664 Rev. *B © ...
Page 23
Document History Page Document Title: CY28435 Clock Generator for Intel Document Number: 38-07664 REV. ECN NO. Issue Date ** 214042 See ECN *A 268575 See ECN *B 305734 See ECN Document #: 38-07664 Rev. *B PRELIMINARY £ Grantsdale Chipset Orig. ...