CY2DL814SI Cypress Semiconductor Corporation., CY2DL814SI Datasheet

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CY2DL814SI

Manufacturer Part Number
CY2DL814SI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
CY2DL814SI
Manufacturer:
CYPRESS
Quantity:
93
Cypress Semiconductor Corporation
Document #: 38-07057 Rev. *B
Features
• Low-voltage operation
• V
• 1:4 Fanout
• Single-input configurable for
• Drives 50- or 100-ohm load (selectable)
• Low input capacitance
• 85 ps typical output-to-output skew
• <4 ns typical propagation delay
• Does not exceed Bellcore 802.3 standards
• Operation at ⇒ 350 MHz – 700 Mbps
• Industrial versions available
• Packages available include TSSOP/SOIC
Block Diagram
— LVDS, LVPECL, or LVTTL
— Four differential pairs of LVDS outputs
DD
CONFIG
IN+
IN-
= 3.3V
EN1
EN2
LVPECL /
LVDS /
LVTTL
CNTRL
3901 North First Street
OUTPUT
LVDS
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Description
The Cypress CY2 series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL814 fanout buffer features a single
LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS
output pairs.
Designed for data-communication clock management applica-
tions, the fanout from a single input reduces loading on the
input clock.
The CY2DL814 is ideal for both level translations from single
ended to LVDS and/or for the distribution of LVDS-based clock
signals. The Cypress CY2DL814 has configurable input and
output
LVPECL/LVTTL or LVDS signals while the output driver’s
support standard and high drive LVDS. Drive either a 50-ohm
or 100-ohm line with a single part number/device.
functions.
Pin Configuration
1:4 Clock Fanout Buffer
San Jose
CONFIG
CNTRL
GND
VDD
EN2
EN1
IN+
IN-
The
,
16-pin TSSOP/SOIC
CA 95134
1
2
3
4
5
6
7
8
input
ComLink™ Series
can
Revised June 20, 2005
16
15
14
13
12
11
10
9
be
CY2DL814
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
selectable
408-943-2600
for
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CY2DL814SI Summary of contents

Page 1

Features • Low-voltage operation • 3.3V DD • 1:4 Fanout • Single-input configurable for — LVDS, LVPECL, or LVTTL — Four differential pairs of LVDS outputs • Drives 50- or 100-ohm load (selectable) • Low input capacitance • ...

Page 2

Pin Description Pin Number Pin Name 6,7 IN+, IN– 3 CNTRL 2 CONFIG 1,8 EN1, EN2 16,15,14,13 Q1A, Q1B, Q2A, 12,11,10,9 Q2B, Q3A, Q3B, Q4A, Q4B Maximum Ratings [1, 2] Storage Temperature: ................................ –65°C ...

Page 3

Table 3. Input Receiver Configuration for Differential or LVTTL/LVCMOS CONFIG Pin 2 Binary Value Input Receiver Family 1 LVTTL in LVCMOS 0 LVDS LVPECL Table 4. Function Control of the TTL Input Logic Used to Accept or Invert the Input ...

Page 4

Table 8. D.C Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input Parameter Description V Input High Voltage IH V Input Low Voltage IL I Input High Current IH I Input Low Current IL I Input High Current I V Clamp Diode Voltage IK V ...

Page 5

Table 12.High Frequency Parametrics Parameter Description Fmax Maximum frequency V = 3.3V DD Fmax(20) Maximum frequency Minimum pulse Pulse Generator B V1A 1 V1B V0Y 1 ...

Page 6

... Figure 4. LVCMOS/LVTTL Single-ended Input Value Ordering Information Part Number CY2DL814ZI CY2DL814ZIT CY2DL814SI CY2DL814SIT CY2DL814ZC CY2DL814ZCT CY2DL814SC CY2DL814SCT Lead-free CY2DL814ZXI CY2DL814ZXIT CY2DL814SXI CY2DL814SXIT CY2DL814ZXC CY2DL814ZXCT ...

Page 7

... ComLink is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07057 Rev. *B © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

Page 8

Document Title: ComLink™ Series CY2DL814 1:4 Clock Fanout Buffer Document Number: 38-07057 Issue REV. ECN NO. Date ** 115362 07/10/02 *A 122744 12/14/02 *B 384077 See ECN Document #: 38-07057 Rev. *B Orig. of Change Description of Change EHX New ...

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