CY2SSTV857ZC-32 Cypress Semiconductor Corporation., CY2SSTV857ZC-32 Datasheet

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CY2SSTV857ZC-32

Manufacturer Part Number
CY2SSTV857ZC-32
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
CY2SSTV857ZC-32
Manufacturer:
CY
Quantity:
3 205
Cypress Semiconductor Corporation
Document #: 38-07557 Rev. *E
Features
• Operating frequency: 60 MHz to 230 MHz
• Supports 400-MHz DDR SDRAM
• 10 differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power management control input
• High-impedance outputs when input clock < 20 MHz
• 2.6V operation
• Pin-compatible with CDC857-2 and -3
• 48-pin TSSOP and 40 QFN package
• Industrial temperature of –40°C to 85°C
• Conforms to JEDEC DDR specification
Block Diagram
AVDD
FBIN#
CLK#
CLK
FBIN
PD
37
16
36
35
13
14
Powerdown
Test and
PLL
Logic
3901 North First Street
10
20
19
22
23
46
47
44
43
39
40
29
30
27
26
32
33
3
2
5
6
9
Y2
Y2#
Y3
Y3#
Y4
Y4#
Y5
Y5#
Y6
Y6#
Y7
Y7#
Y8
Y8#
Y9
Y9#
Y0
Y0#
Y1
Y1#
FBOUT
FBOUT#
Description
The CY2SSTV857-32 is a high-performance, low-skew,
low-jitter zero-delay buffer designed to distribute differential
clocks in high-speed applications. The CY2SSTV857-32
generates ten differential pair clock outputs from one differ-
ential pair clock input. In addition, the CY2SSTV857-32
features differential feedback clock outpts and inputs. This
allows the CY2SSTV857-32 to be used as a zero delay buffer.
When used as a zero delay buffer in nested clock trees, the
CY2SSTV857-32 locks onto the input reference and translates
with near-zero delay to low-skew outputs.
Differential Clock Buffer/Driver
DDR400/PC3200-Compliant
Pin Configuration
VD D Q
VD D Q
VD D Q
VD D Q
VD D Q
AVD D
AVS S
C L K #
VS S
VS S
VS S
C L K
VS S
VS S
Y0 #
Y1 #
Y2 #
Y3 #
Y4 #
San Jose
Y0
Y1
Y2
Y3
Y4
48 TSSOP Package
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
,
CA 95134
Revised January 12, 2005
CY2SSTV857-32
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
VD D Q
VD D Q
Y9 #
Y5 #
Y5
Y6
Y6 #
Y7 #
Y7
Y8 #
Y8
Y9
VS S
VS S
VS S
P D #
FB IN
VS S
VS S
VD D Q
VD D Q
FB IN #
FB O U T #
FB O U T
408-943-2600

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CY2SSTV857ZC-32 Summary of contents

Page 1

Features • Operating frequency: 60 MHz to 230 MHz • Supports 400-MHz DDR SDRAM • 10 differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps • Power management ...

Page 2

Pin Description Pin # Pin # 48 TSSOP 40 QFN 13 10, 20, 22 37,39,3,12, 19, 23 36,40,2,11,15 27, 29, 39, 44, 46 17,19,29,32,34 26, 30, 40, 43, 47 ...

Page 3

Zero Delay Buffer When used as a zero delay buffer the CY2SSTV857-32 will likely nested clock tree application. For these applica- tions, the CY2SSTV857-32 offers a differential clock input pair as a PLL reference. The CY2SSTV857-32 then ...

Page 4

CLKIN Yx or FBIN Yx DDR _SDRAM represents a capacitive load CLK CLK# Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< Document #: 38-07557 Rev Figure 2. Propagation Delay Time t t C(n) ...

Page 5

DDR-SDRAM represents a capacitive load CLK 120 Ohm CLK# 120 Ohm Output load capacitancce for 4 DDR-SDRAM Loads < CL < ...

Page 6

Absolute Maximum Conditions Input Voltage Relative to V :...............................V SS Input Voltage Relative DDQ Storage Temperature: ................................ –65° 150°C Operating Temperature: ................................ –40°C to +85°C Maximum Power Supply: ................................................3.5V DC Electrical Specifications Parameter Description ...

Page 7

... Any Output to Any Output Skew SK(O) [14] t Phase Error PHASE Ordering Information Part Number CY2SSTV857ZC–32 48-pin TSSOP CY2SSTV857ZC–32T 48-pin TSSOP–Tape and Reel [15] CY2SSTV857LFC–32 40-pin QFN [15] CY2SSTV857LFC–32T 40-pin QFN–Tape and Reel CY2SSTV857ZI–32 48-pin TSSOP CY2SSTV857ZI–32T 48-pin TSSOP– ...

Page 8

Package Drawing and Dimension 0.500[0.019 12.395[0.488] 12.598[0.496] 0.500[0.020] 0.851[0.033] BSC 0.950[0.037] TOP VIEW 5.90[0.232] A 6.10[0.240] 5.70[0.224] 5.80[0.228 0.60[0.024] DIA. All product and company names mentioned in this document are the trademarks of their respective ...

Page 9

Document History Page Document Title: CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant Document Number: 38-07557 REV. ECN No. Issue Date ** 128403 08/04/03 *A 129080 09/05/03 *B 130114 10/28/03 *C 210076 See ECN *D 259010 See ECN *E 308437 See ECN Document ...

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