CY7C199L-20ZC Cypress Semiconductor Corporation., CY7C199L-20ZC Datasheet

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CY7C199L-20ZC

Manufacturer Part Number
CY7C199L-20ZC
Description
32K x 8 static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05160 Rev. *B
Features
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CE
WE
• High speed
• Fast t
• CMOS for optimum speed/power
• Low active power
• Low standby power
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in pb-free 28-pin TSOP I and 28-pin (300-Mil)
OE
Logic Block Diagram
— 12 ns
— 495 mW (Max, “L” version)
— 0.275 mW (Max, “L” version)
Molded DIP
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
DOE
INPUT BUFFER
DECODER
COLUMN
ARRAY
32K x 8
POWER
DOWN
198 Champion Court
L
L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Functional Description
The CY7C199 is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and tri-state drivers. This device has
an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
addressed by the address present on the address pins (A
through A
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
0
1
2
3
4
5
6
7
0
through I/O
–12
160
V
12
10
WE
A
A
OE
A
A
A
A
CC
A
A
A
A
A
10
11
14
1
2
3
4
5
6
7
8
9
San Jose
). Reading the device is accomplished by selecting
22
23
24
25
26
27
28
1
2
3
4
5
6
7
Pin Configurations
7
GND
) is written into the memory location
I/O
I/O
I/O
A
A
A
A
A
,
A
A
A
A
A
10
11
12
13
14
5
6
7
8
9
0
1
2
CA 95134-1709
0.05
32K x 8 Static RAM
–15
155
15
90
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
(not to scale)
DIP
Top View
TSOP I
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Revised August 3, 2006
V
WE
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
A
CC
3
2
1
0
4
3
7
6
5
4
–20
150
20
10
CY7C199
408-943-2600
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Unit
mA
mA
ns
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
0
14
13
12
7
6
5
4
3
2
1
0
0
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CY7C199L-20ZC Summary of contents

Page 1

Features • High speed — • Fast t DOE • CMOS for optimum speed/power • Low active power — 495 mW (Max, “L” version) • Low standby power — 0.275 mW (Max, “L” version) • 2V data retention ...

Page 2

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ...

Page 3

Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT AC Test Loads and Waveforms R1 481Ω OUTPUT OUTPUT 255 Ω INCLUDING INCLUDING JIG AND SCOPE (a) Equivalent to: THÉ VENIN EQUIVALENT 167 ...

Page 4

Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data ...

Page 5

Switching Waveforms [12, 13] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [13, 14] Read Cycle No ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT Notes: 12. ...

Page 6

Switching Waveforms (continued) [10, 15, 16] Write Cycle No. 1 (WE Controlled) ADDRESS DATA I/O t HZOE [10, 15, 16] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE DATA I/O Notes: 15. Data I/O ...

Page 7

Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled OE LOW) ADDRESS DATA I/O t HZWE Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1 1.0 0.8 0.6 V =5.0V ...

Page 8

... OE Inputs/Outputs High Data Out Data High Z Ordering Information Speed (ns) Ordering Code 12 CY7C199-12ZXC 15 CY7C199-15ZXC CY7C199L-15ZXC 20 CY7C199-20PXC Document #: 38-05160 Rev. *B (continued) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 V =4.5V 10 =25°C A 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) ...

Page 9

Package Diagrams 14 15 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.090[2.28] 0.110[2.79] LEAD END OPTION (LEAD #1, 14, 15 & 28) Document #: 38-05160 Rev. *B 28-pin (300-Mil) PDIP (51-85014) SEE LEAD END OPTION 1 0.260[6.60] 0.295[7.49] 28 0.030[0.76] 0.080[2.03] SEATING PLANE ...

Page 10

Package Diagrams (continued) 28-pin TSOP Type 1 (8x13.4 mm) (51-85071) All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05160 Rev. *B © Cypress Semiconductor Corporation, 2006. The information contained herein ...

Page 11

Document History Page Document Title: CY7C199 32K x 8 Static RAM Document Number: 38-05160 Issue Orig. of REV. ECN NO. Date Change ** 109971 10/28/01 *A 121730 01/09/02 *B 492500 See ECN Document #: 38-05160 Rev. *B Description of Change ...

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