CY7C4281-10JI Cypress Semiconductor Corporation., CY7C4281-10JI Datasheet
CY7C4281-10JI
Related parts for CY7C4281-10JI
CY7C4281-10JI Summary of contents
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... CY7C4281/91 has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable ...
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... When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected HIGH, the FIFO’s outputs are in High Z (high-impedance) state. CY7C4291 128k x 9 32-pin PLCC 7C4281/91-10 100 0.5 8 Commercial 40 Industrial 45 CY7C4281 CY7C4291 Description 7C4281/91-15 7C4281/91-25 66 ...
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... CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Architecture The CY7C4281/91 consists of an array of 64K to 128K words of nine bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF) ...
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... Full Offset ( default value). Document #: 38-06007 Rev. *C and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4281 (64K-m) and CY7C4291 (128K-m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m ...
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... Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration Document #: 38-06007 Rev. *C RESET (RS) 9 CY7C4281/ Read Enable 2 (REN2) CY7C4281 CY7C4291 READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF ...
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... Com’l Ind Com’l Ind Description Test Conditions MHz 5.0V CC [9, 10] 3.0V R2 GND 680: 1.91V . OHZ CY7C4281 CY7C4291 [4] Ambient Temperature + [ + 40 7C42X110 7C42X115 7C42X125 Min. Max. Min. Max. Min. 2.4 2.4 2.4 ...
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... SKEW2 Almost-Empty Flag and Almost-Full Flag Notes: 11. Pulse widths less than minimum values are not allowed. 12. Values guaranteed by design, not currently tested. Document #: 38-06007 Rev. *C 7C42X1-10 Description Min. 4.5 4.5 0.5 0.5 [12] [12] CY7C4281 CY7C4291 7C42X1-15 7C42X1-25 Max. Min. Max. Min. 100 66 ...
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... NO OPERATION t REF [14] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4281 CY7C4291 ENH NO OPERATION NO OPERATION t WFF t REF VALID DATA t OHZ ...
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... Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. Document #: 38-06007 Rev RSS t RSS t RSS t RSF t RSF t RSF CY7C4281 CY7C4291 t RSR t RSR t RSR [16 Page ...
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... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06007 Rev [18] t FRL t SKEW1 t REF t OLZ t OE (maximum When t < minimum specification, t CLK SKEW2 SKEW1 CY7C4281 CY7C4291 [19 (maximum) = either 2 FRL CLK Page ...
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... FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06007 Rev. *C [18 REF REF t A CY7C4281 CY7C4291 t DS DATA WRITE 2 t ENH t ENS t t ENH ENS [18] t FRL t t SKEW2 DATA READ REF Page ...
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... ENH t A DATA READ t CLKL t t ENS ENH t t ENS ENH Note 21 [20] t PAE , then PAE may not change state until the next RCLK. CY7C4281 CY7C4291 NO WRITE [13] t SKEW1 t t WFF WFF t ENH t ENS t A NEXT DATA READ WORDS Note 22 ...
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... If a write is performed on this rising edge of the write clock, there will be Full (m 1) words of the FIFO when PAF goes LOW. 24. PAF offset = m. 25. 16,384 m words for CY7C4281, 32,768 m words for CY4291. 26 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge ...
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... CLKH RCLK t ENS WEN2/LD t ENS REN1, REN2 Q – Ordering Information 64K x 9 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4281-10JC CY7C4281-10JI 15 CY7C4281-15JC 25 CY7C4281-25JC 128K x 9 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4291-10JC CY7C4291-10JXC CY7C4291-10JI 15 CY7C4291-15JC CY7C4291-15JXC 25 CY7C4291-25JC Document #: 38-06007 Rev CLKL ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 32-Lead Plastic Leaded Chip Carrier J65 CY7C4281 CY7C4291 51-85002-*B ...
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... Document History Page Document Title: CY7C4281, CY7C4291 64K/128K X 9 Deep Sync FIFOs Document Number: 38-06007 REV. ECN NO. Issue Date ** 106468 07/12/01 *A 122259 12/26/02 *B 127854 08/22/03 *C 386004 See ECN Document #: 38-06007 Rev. *C Orig. of Change SZV Change from Spec number: 38-00587 to 38-06007 RBI Power up requirements added to Operating Range Information ...