CY7C63411-PVC Cypress Semiconductor Corporation., CY7C63411-PVC Datasheet
CY7C63411-PVC
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CY7C63411-PVC Summary of contents
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... CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Low-speed USB Peripheral Controller Cypress Semiconductor Corporation Document #: 38-08027 Rev. ** • 3901 North First Street • San Jose CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 • CA 95134 • 408-943-2600 Revised June 4, 2002 ...
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... USB SERIAL INTERFACE ENGINE (SIE) ................................................................................. 20 11.1 USB Enumeration ........................................................................................................................ 20 11.2 PS/2 Operation ............................................................................................................................ 20 11.3 USB Port Status and Control ....................................................................................................... 21 12.0 USB DEVICE ............................................................................................................................... 21 12.1 USB Ports .................................................................................................................................... 21 12.2 Device Endpoints (3) ................................................................................................................... 21 13.0 12-BIT FREE-RUNNING TIMER ................................................................................................. 22 13.1 Timer (LSB) ................................................................................................................................. 22 13.2 Timer (MSB) ................................................................................................................................ 22 14.0 PROCESSOR STATUS AND CONTROL REGISTER ............................................................... 23 15.0 INTERRUPTS .............................................................................................................................. 24 15.1 Interrupt Vectors .......................................................................................................................... 24 Document #: 38-08027 Rev. ** TABLE OF CONTENTS CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... FOR FOR 15.2 Interrupt Latency .......................................................................................................................... 25 15.2.1 USB Bus Reset Interrupt .................................................................................................................... 25 15.2.2 Timer Interrupt .................................................................................................................................... 25 15.2.3 USB Endpoint Interrupts ..................................................................................................................... 25 15.2.4 DAC Interrupt ...................................................................................................................................... 25 15.2.5 GPIO Interrupt .................................................................................................................................... 25 16.0 TRUTH TABLES ......................................................................................................................... 26 17.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................. 29 18.0 DC CHARACTERISTICS ............................................................................................................ 30 19.0 SWITCHING CHARACTERISTICS ............................................................................................. 31 20.0 ORDERING INFORMATION ....................................................................................................... 33 21.0 PACKAGE DIAGRAMS .............................................................................................................. 34 Document #: 38-08027 Rev. ** CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... Table 6-1. I/O Register Summary ........................................................................................................ 14 Table 15-1. Interrupt Vector Assignments ........................................................................................... 24 Table 16-1. USB Register Mode Encoding .......................................................................................... 26 Table 16-2. Decode table forTable 16-3: “Details of Modes for Differing Traffic Conditions” .............. 27 Table 16-3. Details of Modes for Differing Traffic Conditions .............................................................. 28 Document #: 38-08027 Rev. ** LIST OF FIGURES LIST OF TABLES CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... CPU clock • Internal memory — 256 bytes of RAM — 4 Kbytes of EPROM (CY7C63411, CY7C63511) — 6 Kbytes of EPROM (CY7C63412, CY7C63512, CY7C63612) — 8 Kbytes of EPROM (CY7C63413, CY7C63513, CY7C63613) • Interface can auto-configure to operate as PS2 or USB • ...
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... The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller. The CY7C64XX/5XX/6XX are offered with multiple EPROM options to maximize flexibility and minimize cost. The CY7C63411 and the CY7C63511 have 4 Kilobytes of EPROM. The CY7C63412, CY7C63512, and CY7C63612 have 6 Kbytes of EPROM. ...
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... P2[ P2[7] P2[ P1[ P1[ P1[ P3[0] High Current P1[ Outputs P0[ P3[7] P0[ P0[ P0[ DAC[0] PP Vss 20 21 DAC[7] TOP VIEW CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 48-pin SSOP 48-pin SideBraze Vss 2 47 Vss D– P3[ P3[6] P3[7] P3[4] 4 P3[4] P3[5] 45 P3[2] P3[2] P3[ P3[0] P3[0] P3[ P2[6] P2[6] P2[ P2[4] P2[4] P2[ ...
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... DAC I/O Port not bonded out on CY7C63612/13. See note on page 17 for firmware code needed for unused pins 6-MHz ceramic resonator or external clock input 26 14 6-MHz ceramic resonator 23 11 Programming voltage supply, ground during operation 48 24 Voltage supply 24,47 12,23 Ground CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... In normal usage, the constant will be the “base” address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed: Document #: 38-08027 Rev. ** CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... EQU 10h • MOV X,3 • MOV A,[x+array] This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth element would be at address 0x13h. Document #: 38-08027 Rev. ** CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... ASL 1C 4 ASR 1D 5 RLC 1E RRC 1F 4 RET RETI 50-5F 10 80- 90-9F 10 JNC A0-AF 5 JACC B0-BF 5 INDEX CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 address ...
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... USB address A endpoint 2 interrupt vector 0x000E Reserved 0x0010 Reserved 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 0x0018 Reserved 0x001A Program Memory begins here 0x0FFF 0x17FF 6-KB PROM ends here (CY7C63612) ( bytes) 0x1FDF 8-KB PROM ends here (CY7C63613) CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... Data Stack begins here and grows downward The user determines the amount of memory required User Variables 0xE8 USB FIFO for Address A endpoint 2 0xF0 USB FIFO for Address A endpoint 1 0xF8 USB FIFO for Address A endpoint 0 0xFF CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... Watch Dog Reset clear 0x30 R/W DAC I/O 0x31 W Interrupt enable for each DAC pin 0x32 W Interrupt polarity for each DAC pin W One four bit sink current register for each DAC pin 0xFF R/W Microprocessor status and control CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Function [2] [2] [2] Page [2] ...
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... Figure 7-1. Clock Oscillator On-chip Circuit pin if the XTAL pin is left open. Please note that grounding the XTAL IN OUT voltage to the device ramps from internally defined trip voltage (Vrst) CC CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 XTALOUT XTALIN 30 pF has stabilized, then CC Page ...
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... Figure 8-1. Watch Dog Reset (WDR mode 2 bits Q1 Data Out Latch 7 k Port Write Q2 Internal Buffer Port Read to Interrupt Controller Figure 9-1. Block Diagram of a GPIO Line CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Execution begins at Reset Vector 0X00 Q3 GPIO Pin ESD Page ...
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... Figure 9-9. Port 3 Interrupt Enable 0x07h (write only) Document #: 38-08027 Rev. ** P0[4] P0[3] P1[4] P1[3] Figure 9-2. Port 1 Data 0x01h (read/write) P2[4] P2[3] Figure 9-3. Port 2 Data 0x02h (read/write) P3[4] P3[3] Figure 9-4. Port 3 Data 0x03h (read/write) DAC[4] DAC[3] Figure 9-5. DAC Port Data 0x30h (read/write) P0[4] P0[3] P1[4] P1[3] P2[4] P2[3] P3[4] P3[3] CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 P0[2] P0[1] P0[0] P1[2] P1[1] P1[0] P2[2] P2[1] P2[0] P3[2] P3[1] P3[0] High current outputs 3 typical DAC[2] DAC[1] DAC[0] P0[2] P0[1] P0[0] P1[2] ...
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... Pin Interrupt Bit Driver Mode X Resistive 0 CMOS Output 1 Open Drain X Open Drain X Open Drain Port 2 Port 1 Config Bit 0 Config Bit 1 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Interrupt Polarity - disabled disabled - + (default Port 1 Port 0 Port 0 Config Bit 0 Config Bit 1 Config Bit 0 Page ...
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... Isink Isink DAC Register to Interrupt Controller Figure 10-1. Block Diagram of DAC Port DAC[4] DAC[3] Figure 10-2. DAC Port Data 0x30h (read/write) DAC[4] DAC[3] DAC[4] DAC[3] CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 DAC I/O Pin ESD High current outputs 3 typical DAC[2] DAC[1] DAC[0] DAC[2] DAC[1] DAC[0] ...
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... Bits [2:0] defaults to ‘000’ at reset which allows the USB SIE to control output on D+ and D . Firmware can override the SIE and directly control the state of these pins via these 3 control bits. Since PS open drain signaling protocol, these modes allow all 4 PS/2 states to be generated on the D+ and D pins Document #: 38-08027 Rev. ** CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Isink Value ...
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... Force K (D+ HIGH, D– LOW) Force J (D+ LOW, D– HIGH) Force SE0 (D+ LOW, D– LOW) Force SE0 (D LOW, D+ LOW) Force D LOW, D+ HiZ Force D HiZ, D+ LOW Force D HiZ, D+ HiZ Device Device Address Address Bit 4 Bit 3 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/ R/W R/W Control Control Control Bit 2 Bit 1 Control action ...
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... Bit 3 Bit 2 Reserved Byte count Byte count Bit 3 Bit 2 Timer Timer Timer Bit 4 Bit 3 Bit 2 Reserved Timer Timer Bit 11 Bit 10 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Mode Mode Bit 1 Bit 0 Mode Mode Bit 1 Bit 0 Byte count Byte count Bit 1 Bit 0 Timer Timer Bit 1 Bit 0 ...
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... Document #: 38-08027 Rev Figure 13-1. Timer Block Diagram R/W R/W Power-on Suspend, Wait Reset for Interrupt CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 1.024-ms interrupt 128- s interrupt 0 1-MHz clock Timer Register R/W R/W Interrupt Single Step Run Mask Page ...
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... DAC Reserved Interrupt Enable Reserved Reserved ROM Address 0x0000h 0x0002h 0x0004h 0x0006h 0x0008h 0x000Ah 0x000Ch 0x000Eh 0x0010h 0x0012h 0x0014h 0x0016h 0x0018h CY7C63411/12/13 CY7C63511/12/13 CY7C63612/ R/W R/W R/W 1.024-ms 128- sec USB Bus RST Interrupt Interrupt Interrupt Enable Enable Enable 2 1 R/W R/W R/W EPA2 EPA1 ...
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... The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. Document #: 38-08027 Rev. ** CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... This mode is changed by SIE on issuance of ACK --> 1010 NAK ignore An ACK from mode 1101 --> 1100 TX cnt ignore This mode is changed by SIE on issuance of ACK --> 1100 NAK check An ACK from mode 1111 --> 111 Ack In - Status Out TX cnt Check This mode is changed by SIE on issuance of ACK -->1110 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...
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... The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction. Document #: 38-08027 Rev. ** Status bits PID Status bits dval DTOG DVAL COUNT Setup The validity of the received data CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 What the SIE does to Mode bits Interrupt? End Point Mode In Out ACK 3 ...
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... updates updates UC UC CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Set End Point Mode Out ACK response int ACK yes UC UC NoChange ignore yes UC UC NoChange ignore yes UC UC ...
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... CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Set End Point Mode Out ACK response int Stall yes ignore ...
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... Ohms 45% 65 12% V 7.2 16.5 3.5 10.6 1.4 7.5 8.0K 20.0K Ohms 0.1 0.3 0.5 1.5 1.6 4 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Conditions V Non USB activity (note 3) V USB activity (note 5. Oscillator off, D– > Voh min V s Vcc = 5.0V, ceramic resonator Any pin mA Cumulative across all ports (note 10) ms Linear ramp ...
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... To next transition, Figure 19-5 –150 150 ns To paired transition, Figure 19-5 range, as well as DAC outputs. CC (2) of 50–600 pF. LOAD is limited to minimize Ground-Drop noise effects. SS CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Conditions Any pin (note 8,14) Full scale transition (note 14) Vout = 2.0V (note 9,14) Conditions [4, 5] [4, 5] [4, 5] [4, 5] ...
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... Data Lines Document #: 38-08027 Rev CYC Figure 19-1. Clock Timing 90% 90% 10% 10% Figure 19-2. USB Data Signal Timing Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD JR2 Figure 19-3. Receiver Jitter Tolerance CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 T JR1 JR2 Page ...
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... Crossover Differential Data Lines Figure 19-4. Differential to EOP Transition Skew and EOP Width T PERIOD Differential Data Lines 20.0 Ordering Information EPROM Ordering Code Size CY7C63411- CY7C63411-PVC 4 KB CY7C63412- CY7C63412-PVC 6 KB CY7C63413- CY7C63413-PVC 8 KB CY7C63511-PVC 4 KB CY7C63512-PVC 6 KB CY7C63513-PVC 8 KB ...
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... FOR FOR 21.0 Package Diagrams Document #: 38-08027 Rev. ** 48-Lead Shrunk Small Outline Package O48 40-Lead (600-Mil) Molded DIP P17 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 51-85061-*C 51-85019-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 24-Lead (300-Mil) Molded SOIC S13 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 ...
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... FOR FOR Document Title: CY7C63411/12/13, CY7C63511/12/13, CY7C63612/13 Low-speed USB Peripheral Controller Document Number: 38-08027 Issue REV. ECN NO. Date ** 116224 06/12/02 Document #: 38-08027 Rev. ** Orig. of Change Description of Change DSG Change from Spec number: 38-00754 to 38-08027 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Page ...