CYK001M16ZCCAU-70BAI Cypress Semiconductor Corporation., CYK001M16ZCCAU-70BAI Datasheet
CYK001M16ZCCAU-70BAI
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CYK001M16ZCCAU-70BAI Summary of contents
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... CMOS for optimum speed/power • Deep Sleep Mode • Offered in a 48-ball BGA Package Functional Description The CYK001M16ZCCAU is a high-performance CMOS Pseudo static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ ...
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... Product V Range (V) CC Min. Typ. CYK001M16ZCCAU 2.70 3.0 Notes: 2. DNU pins have to be left floating. 3. Ball H6 can be used to upgrade to 32M density “no connect”—not connected internally to the die. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V Document #: 38-05454 Rev ...
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... CC V CCmax OUT CMOS levels −0. 3.3V 100 CC –0.2V, (Address and = 3.30V CC – 0. 3.3V CC – 0. 3.30V ; ZZ = CCMAX CYK001M16ZCCA MoBL3™ ........................................–0.4V to 3.7V [ .....................................–0. 2.70V to 3.30V CYK001M16ZCCAU [5] [5] Max. Min. Typ. Max. Unit 3.0 3.3 2.7 3 – 0.4 0 0.4V V 0.4V CC 0.4 -0.4 0.4 +1 – ...
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Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT [9] Thermal Resistance Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case) AC Test Loads and Waveforms OUTPUT ...
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Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data ...
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Switching Waveforms Read Cycle 1 (Address Transition Controlled) ADDRESS t SK DATA OUT PREVIOUS DATA VALID [14, 16] Read Cycle 2 (OE Controlled) ADDRESS ACE / BHE BLE t LZBE OE t LZOE HIGH IMPEDANCE DATA ...
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Switching Waveforms (continued) [12, 13, 17, 18, 19] Write Cycle 1 (WE Controlled) ADDRESS BHE BLE OE DATA I/O DON’T CARE t HZOE [12, 13, 17, 18, 19] Write Cycle 2 (CE Controlled) ADDRESS CE ...
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Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW) ADDRESS CE / BHE BLE DATAI/O DON’T CARE t Write Cycle 4 (BHE/BLE Controlled, OE LOW) ADDRESS CE BHE/BLE DON’T CARE DATA I/O Document ...
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Deep Sleep Mode This mode can be used to lower the power consumption of the PSRAM in an application. In this mode, the data integrity of the PSRAM is not guaranteed. Deep Sleep Mode can be enabled by driving ZZ ...
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... Ordering Information Speed (ns) Ordering Code 55 CYK001M16ZCCAU-55BAI 70 CYK001M16ZCCAU-70BAI Package Diagram TOP VIEW A1 CORNER 6.00±0.10 B SEATING PLANE C MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. ...
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Document History Page Document Title: CYK001M16ZCCA MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM Document Number: 38-05454 Issue Orig. of REV. ECN NO. Date Change ** 132407 01/27/04 *A 220121 See ECN *B 230851 See ECN Document #: 38-05454 Rev. ...