MN89305 Panasonic, MN89305 Datasheet
MN89305
Related parts for MN89305
MN89305 Summary of contents
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... XGA LCD Display Controller Overview The MN89305 is an LCD display controller IC that provides high-speed graphics and high-quality display. The graphics accelerator supports 3-operand ROP operations and thus can draw Windows quickly. The MN89305 also provides a full complement of power management functions to implement low-power video systems. ...
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... MN89305 Block Diagram PCI/ISA/386/486 HOST I/F WRITE READ FIFO FIFO GRAPHICS BitBLT PATBLT STRING EXTEND 2 HALF FRAME CONTROL GRAY SCALE ENGINE RAM CRTC/LCDC ATT PSCONV VIDEO FIFO MEMORY ACCESS ARBITRATOR MEMORY I/F EDO/Fast Page Mode DRAMs LSIs for Display LCD panel LCD I/F (TFT/SSTN/DSTN) ...
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... PCI 32 bits Furthermore, since the MN89305 supports linear addressing, the CPU address calculation time can be reduced. Thus memory accesses are faster than if memory were accessed using a VGA compatible address area. When the PCI interface is used, only burst transfers are supported for memory transfers. I/O bus transfers must not be done ...
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... MN89305 Block Functional Descriptions (continued) 6) Memory access interface The memory access interface accesses memory according to request signals from the memory access arbitrator. DRAM with fast page mode is used to write display data to memory as quickly as possible. The memory access interface supports variable memory access timings to get the maximum possible speed from memory when fast DRAMs are used. ...
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... VDD VSS 134 135 PLLTEST PLLVSS 136 PLLVDD 137 VDD 138 VSS 139 140 ADS RDY 141 142 BS16 LDEV 143 VREF5 144 (TOP VIEW) MN89305 72 LD4 71 LD5 70 LD6 69 LD7 68 UD0 67 UD1 66 UD2 65 UD3 64 UD4 63 UD5 62 UD6 61 UD7 60 LP ...
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... MN89305 Pin Arrangement (continued) 2) 386SX Local Bus Mode MD6 109 110 MD5 MD4 111 112 MD3 MD2 113 114 MD1 MD0 115 EXTCLK 116 WE 117 CAS3 118 119 CAS2 CAS1 120 121 CAS0 RAS 122 MA9 123 MA8 124 MA7 125 ...
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... VDD VSS 134 135 PLLTEST PLLVSS 136 PLLVDD 137 VDD 138 VSS 139 140 REFRESH IOCHRDY 141 142 IOCS16 MEMCS16 143 VREF5 144 (TOP VIEW) MN89305 72 LD4 71 LD5 70 LD6 69 LD7 68 UD0 67 UD1 66 UD2 65 UD3 64 UD4 63 UD5 62 UD6 61 UD7 60 LP ...
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... MN89305 Pin Arrangement (continued) 4) PCI Bus Mode MD6 109 110 MD5 MD4 111 112 MD3 MD2 113 114 MD1 MD0 115 EXTCLK 116 WE 117 CAS3 118 119 CAS2 CAS1 120 121 CAS0 RAS 122 MA9 123 MA8 124 MA7 125 126 ...
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... Indicates to the host that this chip was accessed as a local bus device. 16-bit data bus Indicates to the host that this chip was accessed as a 16-bit device. Function A high level on this input indicates that a DMA operation is in progress. Therefore, the MN89305 will not respond to an I/O access when this input is high. MN89305 9 ...
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... MN89305 Pin Descriptions (continued) 2) ISA Bus Related Pins (continued) Pin Name I/O Level SBHE TTL System byte high enable IOWR TTL I/O write IORD TTL I/O read MEMW TTL Memory write MEMR TTL Memory read A[ TTL Address[21 : 20] ...
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... Chip select signal of the configuration register. The configuration register can be accessed when this signal is high. If the AD signal is used as IDSEL, we recommend connecting AD24 through AD31. Device select Outputs a low level when an access request to this IC is detected. BIOS chip select Outputs a low level when accepting an access to the video BIOS. MN89305 11 ...
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... MN89305 Pin Descriptions (continued) 3) PCI Bus Related Pins (continued) Due to the differences between the buses, the pin functions correspond as shown in the table. PCI 386SX FRAME A22 CLK CCLK C/BE0 BEL C/BE1 BEH C/BE2 VSS C/BE3 A1 IDSEL A21 BIOSCS A20 VSS A[19 : 17] ...
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... This output is used as the horizontal synchronizing signal when a TFT LCD panel is used or in external RAMDAC mode. Frame pulse Pulse output that indicates the frame start for an STN LCD panel. This output is used as the vertical synchronizing signal when a TFT LCD panel is used or in external RAMDAC mode. MN89305 13 ...
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... MN89305 Pin Descriptions (continued) 5) LCD Related Pins (continued) Pin Name I/O Level DISP O SCK The table below shows the pin functions for each panel type. Pin TFT DISP DEN LP HSYNC FP VSYNC SCK DCLK UD7 R4 UD6 R3 UD5 R2 UD4 R1 UD3 R0 UD2 G5 UD1 ...
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... Used for PLL testing. This pin must be held at the VSS level during normal operation. Function Digital system power supply (3.3 V) Digital system power supply (GND) PLL analog system power supply (3.3 V) PLL analog system power supply (GND input pin power supply (4. 5.25 V) MN89305 15 ...
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... MN89305 Electrical Characteristics 1. Absolute Maximum Ratings at V Parameter Supply voltage † reference voltage Input pin voltage (except TYPE * Input pin voltage (TYPE-A) Input pin voltage (TYPE-B) Input pin voltage (TYPE-C) Output pin voltage (except TYPE * Output pin voltage (TYPE-C) Output current (TYPE-HL1) ...
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... REF5 3.6 V REF5 DD DDPLL V 5.25 V REF5 DD0 MHz, output pins open DDPLL V 5.0 V REF5 MN89305 Min Typ Max 3.0 3.3 3.6 4.75 5.0 5. 100 0 100 4. 5. SSPLL Min Typ Max measurement ...
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... MN89305 Electrical Characteristics (continued Characteristics MHz (continuted) TEST a Parameter Operating supply current Standby mode Operating supply current Suspend mode Operating supply current Sleep mode Oscillator Circuit: XO Internal feedback resistor Oscillator Circuit Input: XIN Input leakage current ...
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... 2 2 High-impedance state MN89305 4. 5. SSPLL Min Typ Max 1.6 2.2 0.6 1.2 0 0.6 DD 0.4 V 0.6 DD 0 0 ...
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... MN89305 Electrical Characteristics (continued Characteristics MHz (continuted) TEST a Parameter I/O with pull-down resisitor (CMOS level): MA3 to MA9 High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Pull-down resistor Output leakage current I/O (TTL level): A20 ...
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... 8 High-impedance state 5. 5. Input Descriptions MN89305 4. 5. SSPLL Min Typ Max 2.0 V REF5 0 0.8 2.4 0 Output Valid data Min Max 4XIN 15 4XIN 15 0 3XIN 12 ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 2) XIN Timing XIN No. 1 XIN rise time (external clock signal mode) 2 XIN fall time (external clock signal mode) 3 XIN high-level period (external clock signal mode) 4 XIN low-level period (external clock signal mode) 5 XIN period Note) The XIN clock determines the memory control timing and the LCD control timing ...
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... Note) 1. †1: CCLK must meet the following condition: (MCLK †2: CCLK must meet the following condition: (MCLK/2) 2. MCLK refers to one clock period of the memory clock. Descriptions Descriptions 5) CCLK (4 5 CCLK (MCLK MN89305 Min Max Unit 20 10 2MCLK 10 4MCLK 10 †2 25 † ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 5) RESET Timing (when a 386 CPU is used) CCLK RESET CLK1X (Internal) (Only in 386 mode) No. 1 RESET hold time 2 RESET setup time 3 RESET high-level period 6) 386CPU RDY# Input and Pipeline Mode Timing CCLK ADS A[ Non VGA ...
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... CLK in the table refers to one clock period of CCLK. 3. Values listed in the table apply when the external load capacitor is 50 pF. The output delay times will differ depending on the external load capacitor CPU WRITE 12 13 Descriptions MN89305 CPU READ Min Max Unit 15 ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 8) 386CPU Local Bus Timing CCLK CCLK1 (Internal M/ ADS 5 BS16 D[ RDY 17 LDEV No. 1 A[23:2], M/IO#, BE[3:0]#, and W/R# setup time 2 A[23:2], M/IO#, BE[3:0]#, and W/R# hold time 3 ADS# setup time 4 ADS# hold time 5 BS16# active delay time 6 BS16# inactive delay time ...
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... AD[31:0] (address) setup time 7 AD[31:0] (address) hold time 8 AD[31:0] (data) setup time 9 AD[31:0] (data) hold time 10 AD[31:0] (data) valid output delay time 11 Time from the TRDY# high-impedance state until drive 33 MHz Descriptions MN89305 Min Max Unit 7 ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 9) PCI Local Bus Timing CLK No. 12 Delay time until TRDY# active 13 Delay time until TRDY# inactive 14 TRDY# high level to high-impedance state transition time 15 Time until DEVSEL# active 16 Time until DEVSEL# inactive 17 DEVSEL# high level to high-impedance state transition time ...
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... Note) 1. CLK in the table is a period time of MCLK in ISA mode, CLK in PCI mode, CCLK in local bus 486 mode, and CCLK in local bus 386 mode. 2. Values listed in the table apply when the external load capacitor is 30 pF. 8 CLK 8 CLK Byte Address 1 Byte Address Descriptions MN89305 8 CLK 8 CLK Data Valid Byte Address 3 4 Min Max 4CLK 10 ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 13) Memory Access Timing (setup procedure) This LSI allows the timing with which DRAM is accessed to be adjusted by setting the memory control expansion registers SR0F and SR11. Set up the optimal cycle timing for the specifications of the DRAM actually used. ...
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... Min EDO ( 101T 6 (Ta Tb) 6 100T ( MN89305 Max Min Max Unit EDO Fast page Fast page mode mode ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 14) Memory Access Timing (continued) No. Descriptions Memory type 10 RAS# address setup time 11 RAS# address hold time 12 CAS# address setup time 13 CAS# address hold time 14 Read command setup time 15 Read command hold time (from CAS#) 16 Read command hold time (from RAS#) ...
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... Values listed in the table apply when the external load capacitor is 30 pF. The output delay times will differ depending on the external load capacitor Min EDO ( Descriptions MN89305 Max Min Max Unit EDO Fast page Fast page mode mode (Ta Tb ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 17) Color STN Two-Screen Panel Timing Line 239 Line 24 LD Line 479 Line 480 LP FP SCK SCK high-level period 2 FP rise to LP fall setup time 3 LP fall to FP fall hold time ...
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... CLK is the display system clock (DCLK). 3. Values listed in the table apply when the external load capacitor is 30 pF. Line 1 Line 2 Line 241 Line 242 Line 243 Descriptions MN89305 Line 3 Line 4 Line 5 Line 244 Line 245 2 3 Min Max †1 8CLK 5 †2 664CLK 10 † ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 19) Color STN Single-Screen Panel Timing Line 479 Line 480 LP FP SCK SCK LD No high-level period 2 FP rise to LP fall setup time 3 LP fall to FP fall hold time 4 SCK fall to LP fall setup time ...
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... When the time from LP completion to the 1 line completion is set character by LCD5 and LCD0. 2. CLK is the display system clock (DCLK). 3. Values listed in the table apply when the external load capacitor is 30 pF. Line 1 Line 2 Line Descriptions MN89305 Line 4 Line Min Max †1 8CLK 5 †2 664CLK 10 †4 8CLK 10 † ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 21) Monochrome STN Single-Screen Panel Timing (4-bit data transfer mode LD Line 479 Line 480 LP FP SCK SCK LD No high-level period 2 FP rise to LP fall setup time 3 LP fall to FP fall hold time ...
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... The XIN duty factor is not taken into consideration when the display clock is set to be the sequencer output. 2. Values listed in the table apply when the external load capacitor Descriptions MN89305 D638 D639 Min Max Unit †2 8DCLK 10 ns †3 1LP ns † ...
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... MN89305 Electrical Characteristics (continued Characteristics (continued) 23) External RAMDAC Mode Timing 1 HSYNC VSYNC HSYNC BLANK P BLANK DCLK P HSYNC VSYNC No. 1 HSYNC low-level period 2 VSYNC low-level period 3 HSYNC period 4 BLANK high-level period 5 DCLK period 6 P[7:0], BLANK, HSYNC, and VSYNC setup time 7 P[7:0], BLANK, HSYNC, and VSYNC hold time Note) 1. † ...
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... LSIs for Display Package Dimensions (Unit: mm) LQFP144-P-2020 108 109 144 1 (1.25) 22.00±0.20 20.00±0. +0.10 0.50 0.20 –0.05 0.10 M 0.10 Seating plane MN89305 (1.00 0.50±0.20 41 ...
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