ICS9176-01 Integrated Device Technology, Inc., ICS9176-01 Datasheet

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ICS9176-01

Manufacturer Part Number
ICS9176-01
Description
Manufacturer
Integrated Device Technology, Inc.
Datasheet
Low Skew Output Buffer
General Description
the ICS9176-01 is designed specifically to support the tight
timing requirements of high-performance microprocessors
and chip sets. Because the jitter of the device is limited to
±250ps, the ICS9176-01 is ideal for clocking Pentium™
systems. The 10 high drive (40mA), low-skew (±250ps)
outputs make the ICS9176-01 a perfect fit for PCI clocking
requirements.
The ICS9176-01 has 10 outputs synchronized in phase and
fre-quency to an input clock. The internal phase locked loop
(PLL) acts either as a 1X clock multiplier or a 1/2X clock
multiplier depending on the state of the input control pins T0
and T1. With metal mask options, any type of ratio between
the input clock and output clock can be achieved, including
2X.
The PLL maintains the phase and frequency relationship be-
tween the input clock and the outputs by externally feeding
back FBOUT to FBIN. Any change in the input will be tracked
by all 10 outputs. However, the change at the outputs will
happen smoothly so no glitches will be present on any driven
input. The PLL circuitry matches rising edges of the input
clock and the output clock. Since the input to FBIN skew is
guaran-teed to ±500ps, the part acts as a “zero delay” buffer.
The ICS9176-01 has a total of eleven outputs. Of these,
FBOUT is dedicated as the feedback into the PLL and another,
Q/2, has an output frequency half that of the remaining nine.
These nine outputs can either be running at the same speed as
the input, or at half the frequency of the input. With Q/2 as the
feedback to FBIN, the nine ‘Q’ outputs will be running at twice
the input frequency in the normal divide-by-1 mode. In this
case, the output can go to 120 MHz with a 60 MHz input clock.
The maximum rise and fall time of an output is 1ns and each is
TTL-compatible with a 40mA symmetric drive.
The ICS9176-01 is fabricated using CMOS technology which
results in much lower power consumption and cost compared
with the gallium arsenide based 1086E. The typical operating
current for the ICS9176-01 is 60mA versus 115mA for the
GA1086E.
ICS9176-01-01RevB061297P
Integrated
Circuit
Systems, Inc.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
Functionality
Features
Block Diagram
FS1
0
0
1
1
ICS9176-01-01 is pin compatible with Triquint GA1086
±500ps skew (max) between input and outputs
±250ps skew (max) between outputs
10 symmetric, TLL-compatible outputs
28-pin PLCC or 28-pin wide SOIC surface mount
package
High drive, 40mA outputs
Power-down option
Output frequency range 20 MHz to 120 MHz
Input frequency range 20 MHz to 100 MHz
Ideal for PCI bus applications
FS0
0
1
0
1
DESCRIPTION
Power-down
Test Mode (PLL Off CLK=outputs)
Normal (PLL On)
Divide by 2 Mode
Pentium is a trademark of Intel Corporation.
ICS9176-01

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ICS9176-01 Summary of contents

Page 1

... TTL-compatible with a 40mA symmetric drive. The ICS9176-01 is fabricated using CMOS technology which results in much lower power consumption and cost compared with the gallium arsenide based 1086E. The typical operating current for the ICS9176-01 is 60mA versus 115mA for the GA1086E. ICS9176-01-01RevB061297P ICS9176-01 Features • ...

Page 2

... ICS9176-01 Pin Configuration 28-Pin PLCC Pin Description PIN NUMBER PIN NAME 1 GND VDD 5 GND VDD 9 CLK 10 FS1 11 FBIN 12 FS0 13 VDD 14 Q/2 15 GND 16 FBOUT VDD 19 GND VDD GND 26 VDD TYPE - GROUND. ...

Page 3

... Timing in Divide by 2 Mode Timing in Eliminate by Test Mode Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage to the device may occur if an output is shorted or forced to ground or VDD. Timing in Power-down Mode 3 ICS9176-01 ...

Page 4

... ICS9176-01 Absolute Maximum Ratings VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V Operating temperature under bias 0°C to +70°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Voltage on I/O pins referenced to GND GND -0.5V to VDD +0.5V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied ...

Page 5

... Note -250 20 For outputs >100 MHz, use 20 Q/2 as feedback Note 2, 4. Input rise time < -500 3ns Note 2, 4. -250 Note ICS9176-01 TYP MAX UNITS - 7 49/ ± ...

Page 6

... In Figure 1, the propagation delay through the divide by 2 circuit is eliminated. The internal phase-locked loop will adjust the output clock on the ICS9176-01 to ensure zero phase delay between the FBIN and CLK signals result, the rising edge at the output of the divide by two circuit will be aligned with the rising edge of the 66 MHz input clock ...

Page 7

... Pattern Number ( digit number for parts with ROM code patterns) Package Type Q=PLCC Device Type (consists digit numbers) Prefix ICS, AV=Standard Device 7 ICS9176-01 PKG. WIDTH OVERALL BOTTOM PKG. WIDTH ±.006 ±.005 ...

Page 8

... ICS9176-01 Ordering Information ICS9176M-01 Example: ICS XXXX- M PPP Pattern Number ( digit number for parts with ROM code patterns) Package Type Device Type (consists digit numbers) Prefix SOIC Package M=SOIC ICS, AV=Standard Device ICS reserves the right to make changes in the device data identified in this publication 8 without further notice ...

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