M30610ECFP Mitsumi Electronics, Corp., M30610ECFP Datasheet
M30610ECFP
Available stocks
Related parts for M30610ECFP
M30610ECFP Summary of contents
Page 1
Description Description The M16C/61 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring ...
Page 2
Description Pin Configuration Figures 1.1.1 and 1.1.2 show the pin configurations (top view). PIN CONFIGURATION (top view ...
Page 3
Description PIN CONFIGURATION (top view ...
Page 4
Description Block Diagram Figure 1.1 block diagram of the M16C/61 group. Block diagram of the M16C/61 group I/O ports Port P0 Internal peripheral functions Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer ...
Page 5
Description Performance Outline Table 1.1 performance outline of M16C/61 group. Table 1.1.1. Performance outline of M16C/61 group Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port P0 to P10 (except P8 Input ...
Page 6
... M30610ECGP M30610ECFS M30610SAFP M30610SAGP M30612SAFP M30612SAGP Note: Do not use the EPROM version for mass production, because tool for program development (for evaluation). 6 M30610ECFP/GP M30612E4FP/GP One-time PROM version EPROM version RAM capacity Package type 32K byte 4K byte 10K byte 64K byte ...
Page 7
Description Type No – Figure 1.1.5. Type No., memory size, and package Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Package type Package ...
Page 8
Pin Description Pin Description Pin name Signal name Power supply input CNV CNV SS SS RESET Reset input X Clock input IN X Clock output OUT BYTE External data bus width select input AV Analog ...
Page 9
Pin Description Pin Description Pin name Signal name I/O port WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY I/O port I/O ...
Page 10
Memory Operation of Functional Blocks The M16C/61 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral ...
Page 11
CPU Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. b15 ...
Page 12
CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction ...
Page 13
CPU • Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when ...
Page 14
Reset Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is ...
Page 15
Reset Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figure 1.6.3 shows the internal status of the microcomputer immediately after the reset is cancelled. Table 1.6.1. Pin status when RESET pin level ...
Page 16
Reset (1) Processor mode register 0 (Note) (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Chip select control register (6) Address match interrupt enable register (7) Protect register (8) Watchdog ...
Page 17
SFR 0000 16 0001 16 0002 16 0003 16 0004 Processor mode register 0 (PM0) 16 0005 Processor mode register 1(PM1) 16 0006 System clock control register 0 (CM0) 16 0007 System clock control register 1 (CM1) 16 0008 Chip ...
Page 18
SFR 0380 Count start flag (TABSR) 16 0381 16 Clock prescaler reset flag (CPSRF) 0382 One-shot start flag (ONSF) 16 0383 Trigger select register (TRGSR) 16 0384 Up-down flag (UDF) 16 0385 16 0386 16 Timer A0 (TA0) 0387 16 ...
Page 19
Software Reset Software Reset Writing “1” to bit 3 of the processor mode register 0 (address 0004 microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved. Processor Mode (1) ...
Page 20
Processor Mode Processor mode register 0 (Note Note 1: Set bit 1 of the protect register (address 000A Note 2: If the V Note 3: Valid in microprocessor and memory expansion ...
Page 21
Processor Mode Single-chip mode 00000 16 SFR area 00400 16 Internal RAM area XXXXX 16 04000 16 Inhibited D0000 16 YYYYY 16 Internal ROM area (Note 2) FFFFF 16 Address Type No. XXXXX 16 M30610M8A 02BFF 16 M30610MAA 02BFF 16 ...
Page 22
Bus Settings Bus Settings The BYTE pin and bits the processor mode register 0 (address 0004 settings. Table 1.10.1 shows the factors used to change the bus settings. Table 1.10.1. Factors for switching bus settings Bus ...
Page 23
Bus Settings Table 1.10.2. Pin functions for each processor mode Single-chip Processor mode mode Multiplexed bus space select bit Data bus width BYTE pin level I/O port I/O port ...
Page 24
Bus Control Bus Control The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. ...
Page 25
Bus Control (3) Read/write signals With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 0004 _____ ________ combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an ...
Page 26
Bus Control ________ (5) The RDY signal ________ RDY is a signal that facilitates access to an external device that requires long access time. As shown in Figure 1.11. “L” is being input to the RDY at the ...
Page 27
Bus Control (6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to __________ the HOLD pin places the microcomputer in the hold state at the end of ...
Page 28
Bus Control (8) BCLK output The user can choose the BCLK output by use of bit 7 of processor mode register 0 (0004 When set to “1”, the output floating. Note: Before attempting to change the contents of the processor ...
Page 29
Bus Control < Separate bus (no wait) > BCLK Write signal Read signal Data bus Address bus Chip select < Separate bus (with wait) > BCLK Write signal Read signal Data bus Address bus Chip select < Multiplexed bus > ...
Page 30
Clock Generating Circuit Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.12.1. Main clock and sub-clock generating circuits Use of clock Usable oscillator ...
Page 31
Clock Generating Circuit Clock Control Figure 1.12.3 shows the block diagram of the clock generating circuit. CM10 “1” Write signal RESET Software reset NMI Interrupt request level judgment output WAIT instruction CM0i : Bit i at address 0006 CM1i : ...
Page 32
Clock Generating Circuit The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided the ...
Page 33
Clock Generating Circuit Figure 1.12.4 shows the system clock control registers 0 and 1. System clock control register 0 (Note Bit symbol Note 1: Set bit 0 of the protect register ...
Page 34
Clock Generating Circuit Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 0006 output from the P5 /CLK C 7 0006 ) is set to “1”, the output of ...
Page 35
Wait Mode Wait Mode When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit ...
Page 36
Status Transition Of BCLK Status Transition Of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.13.4 shows the operating modes corresponding to the settings of system clock control registers 0 ...
Page 37
Power control Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode • High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. ...
Page 38
Power control Transition of stop mode, wait mode All oscillators stopped Stop mode All oscillators stopped Stop mode All oscillators stopped Stop mode Transition of normal mode CM06 = “1” Main clock is oscillating Sub clock is oscillating High-speed mode ...
Page 39
Protection Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.12.6 shows the protect register. The values in the processor mode register ...
Page 40
Interrupt Overview of Interrupt Type of Interrupts Figure 1.13.1 lists the types of interrupts. Software Interrupt Hardware Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 1.13.1. Classification of interrupts • Maskable interrupt ...
Page 41
Interrupt Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow interrupt An overflow interrupt occurs when executing the ...
Page 42
Interrupt Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. • Reset Reset occurs if an “L” is input to the RESET pin. _______ • ...
Page 43
Interrupt Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.13.2 shows ...
Page 44
Interrupt • Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad- dress the INTB ...
Page 45
Interrupt Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a non-maskable interrupt ...
Page 46
Interrupt Interrupt control register Bit symbol Nothing is assigned attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit ...
Page 47
Interrupt Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is ...
Page 48
Interrupt Rewrite the interrupt control register To rewrite the interrupt control register point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control ...
Page 49
Interrupt Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here interrupt occurs during execution of an ...
Page 50
Interrupt Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time ( shown in Table 1.13.5. Table 1.13.5. Time required for executing the interrupt sequence Interrupt ...
Page 51
Interrupt Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, ...
Page 52
Interrupt The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the ...
Page 53
Interrupt Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG was immediately before the start of interrupt sequence and the contents of the ...
Page 54
Interrupt Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 INT2 INT0 Timer B1 Timer A4 Timer A2 UART1 reception UART0 reception UART2 reception A-D conversion DMA1 Bus collision detection Timer A0 UART1 transmission UART0 ...
Page 55
NMI Interrupt ______ INT Interrupt ________ ________ INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. ______ NMI Interrupt ______ An NMI interrupt is generated when the ...
Page 56
Address Match Interrupt Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled ...
Page 57
Precautions for Interrupts Precautions for Interrupts (1) Reading address 00000 • When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt ...
Page 58
Precautions for Interrupts Figure 1.13.12. Switching condition of INT interrupt request (5) Rewrite the interrupt control register • To rewrite the interrupt control register point that does not generate the interrupt request for that register. If ...
Page 59
Watchdog Timer Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog ...
Page 60
Watchdog Timer Watchdog timer control register Watchdog timer start register b7 Figure 1.14.2. Watchdog timer control and start registers 60 b0 Symbol Address WDC 000F 16 Bit symbol Bit name High-order ...
Page 61
DMAC DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right ...
Page 62
DMAC Table 1.15.1. DMAC specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred DMA request factors (Note) Channel priority Transfer unit Transfer address direction Transfer mode DMA interrupt request generation timing When an underflow occurs in ...
Page 63
DMAC DMAi request cause select register Nothing is assigned attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note 1: Address 03B8 ...
Page 64
DMAC DMAi source pointer ( (b19) (b16)(b15) (b23 DMAi destination pointer ( (b19) (b16) (b15) (b23 DMAi transfer counter ( (b15) (b8) b7 ...
Page 65
DMAC (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to ...
Page 66
DMAC (1) 8-bit transfers 16-bit transfers from even address and the source address is even. BCLK Address CPU use bus RD signal WR signal Data CPU use bus (2) 16-bit transfers and the source address is odd Transferring 16-bit data ...
Page 67
DMAC (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.15.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of ...
Page 68
DMAC DMA enable bit Setting the DMA enable bit to 1 makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one ...
Page 69
DMAC (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA ...
Page 70
Timer Timer There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B (three). All these timers function independently. Figure 1.16.1 shows the block diagram of timers 1 ...
Page 71
Timer A Timer A Figure 1.16.2 shows the block diagram of timer A. Figures 1.16.3 to 1.16.5 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai ...
Page 72
Timer A Timer Ai register (Note) (b15) (b8) b7 Count start flag Up/down flag Figure 1.16.4. Timer A-related registers (2) 72 Symbol TA0 TA1 TA2 ...
Page 73
Timer A One-shot start flag Trigger select register Clock prescaler reset flag Figure 1.16.5. Timer A-related ...
Page 74
Timer A (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.16.1.) Figure 1.16.6 shows the timer Ai mode register in timer mode. Table 1.16.1. Specifications of timer mode Item Count source f ...
Page 75
Timer A (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and ...
Page 76
Timer A Table 1.16.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source • Two-phase pulse signals input to TAi Count operation • Up count or down count can ...
Page 77
Timer A Timer Ai mode register (When not using two-phase pulse signal processing Timer Ai mode register (When using two-phase pulse signal processing ...
Page 78
Timer A (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.16.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.16.9 shows the timer Ai mode register ...
Page 79
Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.16.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit ...
Page 80
Timer A Condition : Reload register = 0003 (rising edge of TA Count source “H” TA pin iIN input signal “L” “H” PWM pulse output from TA pin iOUT “L” Timer Ai interrupt “1” request bit “0” Frequency ...
Page 81
Timer B Timer B Figure 1.16.13 shows the block diagram of timer B. Figures 1.16.14 and 1.16.15 show the timer B-related registers. Use the timer Bi mode register ( bits 0 and 1 to choose the ...
Page 82
Timer B Timer Bi register (Note) (b15) (b8 Count start flag Clock prescaler reset flag Figure 1.16.15. Timer B-related registers (2) ...
Page 83
Timer B (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.16.6.) Figure 1.16.16 shows the timer Bi mode register in timer mode. Table 1.16.6. Timer specifications in timer mode Item Count source ...
Page 84
Timer B (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.16.7.) Figure 1.16.17 shows the timer Bi mode register in event counter mode. Table 1.16.7. Timer specifications in ...
Page 85
Timer B (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.16.8.) Figure 1.16.18 shows the timer Bi mode register in pulse period/pulse width measurement ...
Page 86
Timer B When measuring measurement pulse time interval from falling edge to falling edge Count source “H” Measurement pulse “L” Reload register counter transfer timing Timing at which counter reaches “0000 ” 16 “1” Count start flag “0” “1” Timer ...
Page 87
Serial I/O Serial I/O Serial I/O is configured as three channels: UART0, UART1 and UART2. UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.17.1 shows the ...
Page 88
Serial I/O (UART0) RxD 0 Clock source selection f 1 Internal External Clock synchronous type (when internal clock is selected) CLK polarity CLK 0 reversing circuit CTS/RTS selected CTS / RTS 0 0 Vcc CTS0 from ...
Page 89
Serial I/O 1SP SP SP PAR RxDi 2SP 0 0 2SP SP SP PAR 1SP Figure 1.17.2. Block diagram of UARTi ( transmit/receive unit Clock synchronous type UART (7 bits) UART (8 bits) Clock synchronous UART (7 ...
Page 90
Serial I/O No reverse RxD data RxD2 reverse circuit Reverse 1SP SP SP PAR 2SP 2SP SP SP PAR 1SP Figure 1.17.3. Block diagram of UART2 transmit/receive unit 90 Clock synchronous type UART (7 bits) UART Clock ...
Page 91
Serial I/O UARTi transmit buffer register (b15) (b8 UARTi receive buffer register (b15) (b8 UARTi bit rate generator b7 b0 Figure 1.17.4. Serial I/O-related registers (1) Symbol Address When reset U0TB 03A3 , 03A2 ...
Page 92
Serial I/O UARTi transmit/receive mode register UiMR(i=0,1) Bit symbol SMD0 Serial I/O mode select bit SMD1 SMD2 CKDIR STPS PRY PRYE SLEP UART2 transmit/receive mode register ...
Page 93
Serial I/O UARTi transmit/receive control register Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. ...
Page 94
Serial I/O UARTi transmit/receive control register UiC1(i=0,1) Bit symbol Nothing is assigned attempt to write to these bits, write “0”. The value, if read, turns ...
Page 95
Serial I/O UART transmit/receive control register Bit symbol U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1 RCSP Nothing is assigned attempt to write to this bit, write “0”. The value, if ...
Page 96
Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.17.2 and table 1.17.3 list the specifications of the clock synchronous serial I/O ...
Page 97
Clock synchronous serial I/O mode Table 1.17.3. Specifications of clock synchronous serial I/O mode (2) Item Select function • CLK polarity selection • LSB first/MSB first selection • Continuous receive mode selection • Transfer clock output from multiple pins selection ...
Page 98
Clock synchronous serial I/O mode UARTi transmit/receive mode registers UART2 transmit/receive mode register Figure 1.17.9. UARTi ...
Page 99
Clock synchronous serial I/O mode Table 1.17.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/ _______ RTS ...
Page 100
Clock synchronous serial I/O mode • Example of transmit timing (when internal clock is selected) Transfer clock “1” Transmit enable “0” Data is set in UARTi transmit buffer register bit (TE) “1” Transmit buffer empty flag (Tl) “0” “H” CTSi ...
Page 101
Clock synchronous serial I/O mode (a) Polarity select function As shown in Figure 1.17.11, the CLK polarity select bit (bit 6 at addresses 03A4 allows selection of the polarity of the transfer clock. • When CLK polarity select bit = ...
Page 102
Clock synchronous serial I/O mode (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS ...
Page 103
Clock asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 1.17.5 and table 1.17.6 list the specifications of ...
Page 104
Clock asynchronous serial I/O (UART) mode Table 1.17.6. Specifications of UART Mode (2) Item Select function • Separate CTS/RTS pins (UART0) • Sleep mode selection (UART0, UART1) • Serial data logic switch (UART2) • T 104 Specification _______ _______ _______ ...
Page 105
Clock asynchronous serial I/O (UART) mode UARTi transmit / receive mode registers UART2 transmit / receive mode register Figure 1.17.15. UARTi transmit/receive mode ...
Page 106
Clock asynchronous serial I/O (UART) mode Table 1.17.7 lists the functions of the input/output pins during UART mode. This table shows the pin functions when the separate CTS/RTS pins function is not selected. Note that for a period from when ...
Page 107
Clock asynchronous serial I/O (UART) mode • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock “1” Transmit enable bit(TE) “0” “1” Transmit buffer empty flag(TI) “0” “H” CTSi “L” Start ...
Page 108
Clock asynchronous serial I/O (UART) mode Transfer clock “1” Transmit enable bit(TE) Data is set in UART2 transmit buffer register “0” Transmit buffer “1” empty flag(TI) “0” Start bit TxD “1” Transmit register empty flag (TXEPT) “0” ...
Page 109
Clock asynchronous serial I/O (UART) mode • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source “1” Receive enable bit “0” RxDi Transfer clock Reception triggered when transfer clock “1” ...
Page 110
Clock asynchronous serial I/O (UART) mode (c) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D transmission buffer register or reading the reception buffer register. Figure 1.17.20 shows the ex- ample ...
Page 111
Clock asynchronous serial I/O (UART) mode (3) Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial ...
Page 112
Clock asynchronous serial I/O (UART) mode Transfer clock “1” Transmit enable bit(TE) “0” “1” Transmit buffer empty flag(TI) “0” Start bit TxD 2 ST RxD 2 Signal conductor level ST (Note 1) Transmit register “1” empty flag (TXEPT) “0” “1” ...
Page 113
Clock asynchronous serial I/O (UART) mode (a) Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D level from the T D pin when a parity error is detected. In step ...
Page 114
Clock asynchronous serial I/O (UART) mode Figure 1.17.25 shows the example of connecting the SIM interface. Connect T up. Figure 1.17.25. Connecting the SIM interface 114 Microcomputer TxD 2 RxD 2 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS ...
Page 115
A-D Converter A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P10 to P10 , these pins for A-D conversion must therefore be set to input. ...
Page 116
A-D Converter f AD 1/2 V REF VCUT=0 Resistor ladder AV SS VCUT=1 Successive conversion register Addresses (03C1 , 03C0 ) A-D register 0(16 (03C3 , 03C2 ) 16 16 A-D register 1(16) (03C5 , 03C4 ) A-D ...
Page 117
A-D Converter A-D control register 0 (Note Bit symbol Note: If the A-D control register is rewritten during A-D conversion, the conversion result is A-D control register 1 (Note ...
Page 118
A-D Converter A-D control register 2 (Note Bit symbol Reserved bit Nothing is assigned attempt to write to these bits, write “0”. The value, if read, turns ...
Page 119
A-D Converter (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver- sion. Table 1.18.2 shows the specifications of one-shot mode. Figure 1.18.4 shows the A-D control regis- ...
Page 120
A-D Converter (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.18.3 shows the specifications of repeat mode. Figure 1.18.5 shows the A-D control register in ...
Page 121
A-D Converter (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.18.4 shows the specifications of single sweep mode. Figure 1.18.6 shows the A-D ...
Page 122
A-D Converter (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.18.5 shows the specifications of repeat sweep mode 0. Figure ...
Page 123
A-D Converter (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.18.6 shows the specifications of ...
Page 124
A-D Converter (a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D4 sample and hold is selected, the rate of conversion of each pin increases result, a ...
Page 125
D-A Converter D-A Converter This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 ...
Page 126
D-A Converter D-A control register Nothing is assigned attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. D-A register b7 b0 Figure ...
Page 127
CRC CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom- puter uses a generator polynomial of CRC_CCITT (X The CRC code is a 16-bit code generated for a block of a ...
Page 128
CRC b15 (1) Setting 0000 16 (2) Setting 01 16 b15 The code resulting from sending 1), becomes the remainder resulting from dividing (1000 0000) X conformity with the modulo-2 ...
Page 129
Programmable I/O Port Programmable I/O Ports There are 87 programmable I/O ports P10 (excluding P8 input or output using the direction register. A pull-up resistance for each block of 4 ports can be set input-only port ...
Page 130
Programmable I/O Port ...
Page 131
Programmable I/O Port Data bus Input to respective peripheral functions P7 0 Data bus P7 1 Data bus Input to respective peripheral functions P8 5 Data bus Note not apply a voltage ...
Page 132
Programmable I/O Port P10 to P10 (inside dotted-line not included) P10 to P10 4 7 (inside dotted-line included) Data bus Data bus Figure 1.21.3. Programmable I/O ports ...
Page 133
Programmable I/O Port Direction register P8 7 Data bus Input to respective peripheral functions P8 Direction register 6 Data bus Figure 1.21.4. Programmable I/O ports (4) BYTE BYTE signal input CNV SS CNV signal input SS RESET RESET signal input ...
Page 134
Programmable I/O Port Port Pi direction register (Note PDi ( 10, except 8) Bit symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Note: Set bit 2 of protect ...
Page 135
Programmable I/O Port Port Pi register 10, except 8) Bit symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Note : Since P7 Port P8 register b7 ...
Page 136
Programmable I/O Port Pull-up control register Bit symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Pull-up control register Bit symbol PU10 ...
Page 137
Programmable I/O Port Table 1.21.1. Example connection of unused pins in single-chip mode Pin name Ports P0 to P10 (excluding (Note) OUT NMI BYTE SS REF CNV SS Note: With ...
Page 138
Usage precaution Usage Precaution Timer A (timer mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets ...
Page 139
Usage precaution Timer B (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is ...
Page 140
Usage precaution _______ (3) The NMI interrupt _______ • As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the V resistor (pull-up) if unused. Be sure to work on it. • Do not get either ...
Page 141
... Be especially careful during power-on. (2) One Time PROM version One Time PROM versions shipped in blank (M30612E4FP, M30612E4GP, M30610ECFP, M30610ECGP), of which built-in PROMs are programmed by users, are also provided. For these microcomputers, a programming test and screening are not performed in the assembly process and the following processes ...
Page 142
Items to be submitted when ordering masked ROM version Please submit the following when ordering masked ROM products: (1) Mask ROM confirmation form (2) Mark specification sheet (3) ROM data : EPROMs or floppy disks *: In the case of ...
Page 143
Electrical characteristics Table 1.24.1. Absolute maximum ratings Parameter Symbol Vcc Supply voltage AVcc Analog supply voltage Input voltage RESET ...
Page 144
Electrical characteristics (Vcc = 5V) Table 1.24.2. Recommended operating conditions (referenced – Symbol Supply voltage Vcc AVcc Analog supply voltage Supply voltage Vss Analog supply voltage AVss V HIGH input voltage IH ...
Page 145
Electrical characteristics (Vcc = 5V) Table 1.24.3. Electrical characteristics (referenced to V 10MH unless otherwise specified) Z Symbol Parameter HIGH output voltage ...
Page 146
Electrical characteristics (Vcc = 5V) Table 1.24.4. A-D conversion characteristics (referenced Symbol Parameter Resolution Absolute Sample & hold function not available accuracy Sample & hold function available(10bit) Sample & hold function available(8bit) R ...
Page 147
Timing (Vcc = 5V) Timing requirements (referenced to V Table 1.24.6. External clock input Symbol t External clock input cycle time External clock input HIGH pulse width w(H t External clock input LOW pulse width w(L) t ...
Page 148
Timing (Vcc = 5V) Timing requirements (referenced to V Table 1.24.8. Timer A input (counter input in event counter mode) Symbol t c(TA) TAi input cycle time IN t TAi input HIGH pulse width w(TAH TAi input LOW ...
Page 149
Timing (Vcc = 5V) Timing requirements (referenced to V Table 1.24.13. Timer B input (counter input in event counter mode) Symbol t TBi input cycle time (counted on one edge) c(TB TBi input HIGH pulse width (counted on ...
Page 150
Timing (Vcc = 5V) Switching characteristics (referenced to V otherwise specified) Table 1.24.19. Memory expansion mode and microprocessor mode (no wait) Symbol t Address output delay time d(BCLK-AD) t Address output hold time (BCLK standard) h(BCLK-AD) t Address output hold ...
Page 151
Timing (Vcc = 5V) Switching characteristics (referenced to V otherwise specified) Table 1.24.20. Memory expansion mode and microprocessor mode (with wait, accessing external memory) Symbol t Address output delay time d(BCLK-AD) t Address output hold time (BCLK standard) h(BCLK-AD) t ...
Page 152
Timing (Vcc = 5V) Switching characteristics (referenced to V otherwise specified) Table 1.24.21. Memory expansion mode and microprocessor mode (with wait, accessing external memory, multiplex bus area selected) Symbol Parameter t Address output delay time d(BCLK-AD) t Address output hold ...
Page 153
Timing (Vcc = 5V) Figure 1.24.1. Port P0 to P10 measurement circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 30pF P10 Mitsubishi microcomputers M16C / 61 Group 153 ...
Page 154
Timing (Vcc = 5V) TAi input IN TAi input OUT TAi input OUT (Up/down input) During event counter mode TAi input IN (When count on falling edge is selected) TAi input IN (When count on rising edge is selected) TBi ...
Page 155
Timing (Vcc = 5V) Memory Expansion Mode and Microprocessor Mode (Valid only with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input (Valid with or without wait) BCLK t ...
Page 156
Timing (Vcc = 5V) Memory Expansion Mode and Microprocessor Mode (With no wait) Read timing BCLK t d(BCLK–CS) 25ns.max CSi tcyc t d(BCLK–AD) 25ns.max ADi BHE t t d(BCLK–ALE) h(BCLK–ALE) 25ns.max ALE t d(BCLK–RD) 25ns.max RD Hi– SU(DB–RD) ...
Page 157
Timing (Vcc = 5V) Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Read timing BCLK t d(BCLK–CS) 25ns.max CSi tcyc t d(BCLK–AD) 25ns.max ADi BHE t d(BCLK–ALE) 25ns.max ALE RD DB Write timing BCLK t ...
Page 158
Timing (Vcc = 5V) Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait, and select multiplexed bus) Read timing BCLK t d(BCLK–CS) 25ns.max CSi t d(AD–ALE) (tcyc/2-25)ns.min ADi /DBi t d(BCLK–AD) 25ns.max ADi BHE t d(BCLK–ALE) ...
Page 159
Electrical characteristics (Vcc = 3V) Table 1.24.22. Electrical characteristics (referenced to V 7MH with wait) Z, Symbol Parameter HIGH output voltage ,P8 , ...
Page 160
Timing (Vcc = 3V) Table 1.24.23. A-D conversion characteristics (referenced Symbol Parameter Resolution Absolute accuracy Sample & hold function not available (8 bit) R Ladder resistance LADDER Conversion time t (8bit) CONV V ...
Page 161
Timing (Vcc = 3V) Timing requirements (referenced to V Table 1.24.25. External clock input Symbol t External clock input cycle time External clock input HIGH pulse width w(H t External clock input LOW pulse width w(L) t ...
Page 162
Timing (Vcc = 3V) Timing requirements (referenced to V Table 1.24.27. Timer A input (counter input in event counter mode) Symbol t TAi input cycle time c(TA TAi input HIGH pulse width w(TAH TAi input LOW ...
Page 163
Timing (Vcc = 3V) Timing requirements (referenced to V Table 1.24.32. Timer B input (counter input in event counter mode) Symbol t TBi input cycle time (counted on one edge) c(TB TBi input HIGH pulse width (counted on ...
Page 164
Timing (Vcc = 3V) Switching characteristics (referenced to V otherwise specified) Table 1.24.38. Memory expansion and microprocessor modes (with no wait) Symbol Parameter t Address output delay time d(BCLK-AD) t Address output hold time (BCLK standard) h(BCLK-AD) t Address output ...
Page 165
Timing (Vcc = 3V) Switching characteristics (referenced to V otherwise specified) Table 1.24.39. Memory expansion and microprocessor modes (when accessing external memory area with wait) Symbol Parameter t Address output delay time d(BCLK-AD) t Address output hold time (BCLK standard) ...
Page 166
Timing (Vcc = 3V) Switching characteristics (referenced to V otherwise specified) Table 1.24.40. Memory expansion and microprocessor modes (when accessing external memory area with wait, and select multiplexed bus) Symbol Parameter t Address output delay time d(BCLK-AD) t Address output ...
Page 167
Timing (Vcc = 3V) TAi input IN TAi input OUT TAi input OUT (Up/down input) During event counter mode TAi input IN (When count on falling edge is selected) TAi input IN (When count on rising edge is selected) TBi ...
Page 168
Timing (Vcc = 3V) Memory Expansion Mode and Microprocessor Mode (Valid only with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input (Valid with or without wait) BCLK t ...
Page 169
Timing (Vcc = 3V) Memory Expansion Mode and Microprocessor Mode (With no wait) Read timing BCLK t d(BCLK–CS) 60ns.max CSi tcyc t d(BCLK–AD) 60ns.max ADi BHE t t h(BCLK–ALE) d(BCLK–ALE) 60ns.max ALE t d(BCLK–RD) 60ns.max RD Hi–Z DB Write timing ...
Page 170
Timing (Vcc = 3V) Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Read timing BCLK t d(BCLK–CS) 60ns.max CSi tcyc t d(BCLK–AD) 60ns.max ADi BHE t d(BCLK–ALE) 60ns.max ALE RD DB Write timing BCLK t ...
Page 171
Timing (Vcc = 3V) Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait, and select multiplexed bus) Read timing BCLK t d(BCLK–CS) 60ns.max CSi t d(AD–ALE) (tcyc/2–60)ns.min ADi /DBi t h(ALE–AD) 50ns.min t d(BCLK–AD) 60ns.max ADi ...
Page 172
GZZ SH11 53B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610M8A-XXXFP/GP MASK ROM CONFIRMATION FORM Company name Customer Date Date : issued 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If ...
Page 173
GZZ SH11 53B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610M8A-XXXFP/GP MASK ROM CONFIRMATION FORM The ASCII code for the type No. can be written to EPROM addresses 00000 pseudo-instructions for the respective EPROM type shown in the following table at ...
Page 174
GZZ SH11 53B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610M8A-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of X CIN Ceramic resonator External clock input What frequency do you use? f CIN (3) Which operation mode do you ...
Page 175
GZZ SH11 52B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MAA-XXXFP/GP MASK ROM CONFIRMATION FORM Company name Customer Date Date : issued 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If ...
Page 176
GZZ SH11 52B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MAA-XXXFP/GP MASK ROM CONFIRMATION FORM The ASCII code for the type No. can be written to EPROM addresses 00000 pseudo-instructions for the respective EPROM type shown in the following table at ...
Page 177
GZZ SH11 52B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MAA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind CIN Ceramic resonator External clock input What frequency do you use? f CIN (3) Which operation mode do ...
Page 178
GZZ SH11 51B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MCA-XXXFP/GP MASK ROM CONFIRMATION FORM Company name Customer Date Date : issued 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If ...
Page 179
GZZ SH11 51B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MCA-XXXFP/GP MASK ROM CONFIRMATION FORM The ASCII code for the type No. can be written to EPROM addresses 00000 pseudo-instructions for the respective EPROM type shown in the following table at ...
Page 180
GZZ SH11 51B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MCA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of X CIN Ceramic resonator External clock input What frequency do you use? f CIN (3) Which operation mode do you ...
Page 181
GZZ SH12 35B <79A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M4A-XXXFP/GP MASK ROM CONFIRMATION FORM Company name Customer Date Date : issued 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If ...
Page 182
GZZ SH12 35B <79A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M4A-XXXFP/GP MASK ROM CONFIRMATION FORM The ASCII code for the type No. can be written to EPROM addresses 00000 pseudo-instructions for the respective EPROM type shown in the following table at ...
Page 183
GZZ SH12 35B <79A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M4A-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind CIN Ceramic resonator External clock input What frequency do you use? f CIN (3) Which operation mode do ...
Page 184
GZZ SH12 34B <79A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M8A-XXXFP/GP MASK ROM CONFIRMATION FORM Company name Customer Date Date : issued 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If ...
Page 185
GZZ SH12 34B <79A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M8A-XXXFP/GP MASK ROM CONFIRMATION FORM The ASCII code for the type No. can be written to EPROM addresses 00000 pseudo-instructions for the respective EPROM type shown in the following table at ...
Page 186
GZZ SH12 34B <79A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M8A-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of X CIN Ceramic resonator External clock input What frequency do you use? f CIN (3) Which operation mode do you ...
Page 187
GZZ SH12 55B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MAA-XXXFP/GP MASK ROM CONFIRMATION FORM Company name Customer Date Date : issued 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If ...
Page 188
GZZ SH11 55B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MAA-XXXFP/GP MASK ROM CONFIRMATION FORM The ASCII code for the type No. can be written to EPROM addresses 00000 pseudo-instructions for the respective EPROM type shown in the following table at ...
Page 189
GZZ SH11 55B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MAA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind CIN Ceramic resonator External clock input What frequency do you use? f CIN (3) Which operation mode do ...
Page 190
GZZ SH11 54B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MCA-XXXFP/GP MASK ROM CONFIRMATION FORM Company name Customer Date Date : issued 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If ...
Page 191
GZZ SH11 54B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MCA-XXXFP/GP MASK ROM CONFIRMATION FORM The ASCII code for the type No. can be written to EPROM addresses 00000 pseudo-instructions for the respective EPROM type shown in the following table at ...
Page 192
GZZ SH11 54B <71A1> MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MCA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of X CIN Ceramic resonator External clock input What frequency do you use? f CIN (3) Which operation mode do you ...
Page 193
EIAJ Package Code JEDEC Code QFP100-P-1420-0.65 – 100 100P6Q-A EIAJ Package Code JEDEC Code LQFP100-P-1414-0.50 – 100 ...
Page 194
Differences between M16C/61 group and M30600M8 Type name ROM See Figure 4. ROM Expansion Internal memory size RAM Chip select CS0 30000 CS1 28000 CS2 08000 CS3 04000 SFR area 00000 Internal area on memory RAM area 00400 expansion mode ...
Page 195
Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 195 ...
Page 196
Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to ...
Page 197
MITSUBISHI SEMICONDUCTORS M16C/61 Group Specification REV.E Apr. First Edition 1999 Editioned by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of ...