DP83846 National Semiconductor, DP83846 Datasheet
DP83846
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DP83846 Summary of contents
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... DP83846A DsPHYTER General Description The DP83846A is a full feature single Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols over Cat- egory 3 (10 Mb/s) or Category 5 unshielded twisted pair cables. The DP83846A is designed for easy implementation of 10/100 Mb/s Ethernet home or office solutions. It interfaces to Twisted Pair media via an external transformer ...
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HARDWARE CONFIGURATION PINS (AN_EN, AN0, AN1) (PAUSE_EN) (LED_CFG, PHYAD) TX_DATA TX_DATA TRANSMIT CHANNELS & STATE MACHINES 100 Mb/s 10 Mb/s 4B/5B ENCODER NRZ TO MANCHESTER PARALLEL TO ENCODER SERIAL SCRAMBLER LINK PULSE GENERATOR NRZ TO NRZI ENCODER TRANSMIT BINARY TO ...
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Table of Contents 1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MII ...
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... RESERVED 68 RESERVED 69 RESERVED 70 RESERVED 71 CORE_VDD 72 CORE_GND 73 RESERVED 74 RESERVED 75 SUB_GND 76 RESERVED 77 RESERVED 78 SUB_GND 79 RESERVED 80 DP83846A DSPHYTER Plastic Quad Flat Package JEDEC (LQFP) Order Number DP83846AVHG NS Package Number VHG80A 4 RXD_1 40 RXD_2 39 RXD_3 38 MDC 37 MDIO 36 IO_VDD 35 IO_GND 34 LED_DPLX/PHYAD0 33 LED_COL/PHYAD1 32 LED_GDLNK/PHYAD2 31 LED_TX/PHYAD3 30 LED_RX/PHYAD4 29 LED_SPEED 28 AN_EN ...
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... MDC MDIO CRS/LED_CFG COL TX_CLK TXD[3] TXD[2] TXD[1] TXD[0]] TX_EN TX_ER All DP83846A signal pins are I/O cells regardless of the particular use. Below definitions define the functionality of the I/O cells for each pin. Type: I Type: O Type: I/O Type OD Type: PD,PU Internal Pulldown/Pullup Type: S Type Pin # ...
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... Auto-Negotiation. I 10, 11 Differential receive input. These differential inputs can be configured to accept either 100BASE-TX or 10BASE-T sig- naling. The DP83846A will automatically configure the receive in- puts to accept the proper signal type as a result of either forced configuration or Auto-Negotiation. 6 Description www.national.com ...
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... Type Pin # I 67 REFERENCE CLOCK INPUT 25 MHz: This pin is the pri- mary clock reference input for the DP83846A and must be connected MHz 0.005 ppm) clock source. The DP83846A supports CMOS-level oscillator sources REFERENCE CLOCK OUTPUT 25 MHz: This pin is the primary clock reference output ...
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... GND ( These pins should NEVER be connected directly to GND or V CC. The value set at this input is latched into the DP83846A at Hardware-Reset. The float/pull-down status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Ad- vertisement Register during Hardware-Reset. After reset is ...
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... I 62 RESET: Active Low input that initializes or re-initializes the DP83846A. Asserting this pin low for at least 160 s will force a reset process to occur which will result in all internal registers re-initializing to their default states as specified for each bit in the Register Block section and all strapping op- tions are re-initialized ...
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Package Pin Assignments Pin # Pin Name 1 RESERVED 2 ANA_GND 3 RBIAS 4 ANA_VDD 5 RESERVED 6 ANA_GND 7 ANA_VDD 8 RESERVED 9 ANA_GND 10 RD- 11 RD+ 12 ANA_VDD 13 ANA_GND 14 ANA_VDD 15 ANA_GND 16 TD+ ...
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... Duplex, and Full Duplex modes may be selected. The BMCR provides software with a mechanism to control the operation of the DP83846A. The AN0 and AN1 pins do not affect the contents of the BMCR and cannot be used by software to obtain status of the mode selected. Bits 1 & the PHYSTS register are only valid if Auto-Negotiation is disabled or after Auto-Negotiation is complete ...
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... The DP83846A can be set to respond to any of 32 possible PHY addresses. Each DP83846A or port sharing an MDIO bus in a system must have a unique physical address. Refer to Section 3.1.4, PHY Address Sensing section for more details. The state of each of the PHYAD inputs latched into the ...
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... PHYAD4= 0 Figure 2. PHYAD Strapping and LED Loading Example 2.3 LED INTERFACES The DP83846A has 6 Light Emitting Diode (LED) outputs to indicate the status of Link, Transmit, Receive, Collision, Speed, and Full/Half Duplex operation. The LED_CFG strap option is used to configure the LED_FDPLX output for use as an LED driver or more general purpose control pin ...
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... Mb/s). 2.5 MII Isolate Mode The DP83846A can be put into MII Isolate mode by writing to bit 10 of the BMCR register. In addition, the MII isolate mode can be selected by strapping in Physical Address 0. ...
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... IDLE and turnaround, will pull MDIO high. In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83846A with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 consecu- ...
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... Collisions are reported by the COL signal on the MII. If the DP83846A is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network ...
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... MAC, the code-group encoder injects the T/R code-group pair (01101 00111) indicating the end of frame. After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream DP83846A implements the 100BASE-TX transmit state machine diagram as specified in the IEEE 802.3u Stan- dard, Clause 24. TX_CLK ...
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... The DP83846A uses the PHY_ID (pins PHYAD [4:0]) to set a unique seed value. 3.2.3 NRZ to NRZI Encoder After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX trans- mission over Category-5 Unsheilded twisted pair cable ...
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Table 5. 4B5B Code-Group Encoding/Decoding Name PCS 5B Code-group DATA CODES IDLE AND CONTROL CODES INVALID CODES V ...
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... Input and Base Line Wander Compensation Unlike the DP83223V Twister, the DP83846A requires no external attenuation circuitry at its receive inputs, RD accepts TP-PMD compliant waveforms directly, requiring only a 100 termination plus a simple 1:1 transformer. ...
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RX_CLK 5 BP_4B5B 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT BP_SCR DESCRAMBLER CLOCK NRZI TO NRZ CLOCK DECODER RECOVERY MODULE MLT-3 TO BINARY DECODER DIGITAL ADAPTIVE EQUALIZATION AGC INPUT BLW COMPENSATION ADC RD Figure 8. Receive Block Diagram RXD[3:0] ...
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... This approach will typically leave holes at certain cable lengths, where the performance of the equalizer is not optimized. The DP83846A equalizer is truly adaptive to any length of cable up to 150m. 3.3.4 Clock Recovery Module The Clock Recovery Module (CRM) accepts 125 Mb/s MLT3 data from the equalizer ...
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... In Half Duplex mode the DP83846A functions as a stan- dard IEEE 802.3 10BASE-T transceiver supporting the CSMA/CD protocol. Full Duplex Mode In Full Duplex mode the DP83846A is capable of simulta- neously transmitting and receiving without asserting the collision signal. The DP83846A's 10 Mb/s ENDEC is designed to encode and decode simultaneously. ...
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... Correction not be disabled during normal opera- tion. 3.4.7 Transmit and Receive Filtering External 10BASE-T filters are not required when using the DP83846A, as the required signal conditioning is inte- grated into the device. Only isolation/step-up transformers and impedance match- ing resistors are required for the 10BASE-T transmit and receive interface. The internal transmit fi ...
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... SIDE OF THE ISOLATION TRANSFORMER RX Figure 10. Typical DP83846A Network Interface with additional ESD protection For applications where high reliability is required rec- ommended that additional ESD protection diodes be added as shown below. There are numerous dual series con- nected diode pairs that are available specifically for ESD protection ...
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... If a crystal is specified for a lower drive level, a current lim- iting resistor should be placed in series between X2 and the crystal. 4.0 Reset Operation The DP83846A can be reset either by hardware or soft- ware. A hardware reset may be accomplished by asserting the RESET pin after powering up the device (this is required) or during normal operation when a reset is needed ...
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Register Block Offset Access Hex Decimal 00h 0 RW 01h 1 RO 02h 2 RO 03h 3 RO 04h 4 RW 05h 5 RW 05h 5 RW 06h 6 RW 07h 7 RW 08h-Fh 8-15 10h 16 RO 11h-13h ...
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Register Name Addr Basic Mode Control Register 00h BMCR Basic Mode Status Register 01h BMSR PHY Identifier Register 1 02h PHYIDR1 PHY Identifier Register 2 03h PHYIDR2 Auto-Negotiation Advertisement Register 04h ANAR Auto-Negotiation Link Partner Ability Regis- 05h ANLPAR ter ...
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Register Definition In the register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access SC — =Register sets on event occurrence and Self-Clears when event ends — RW/SC =Read Write access/Self Clearing bit — ...
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Table 7. Basic Mode Control Register (BMCR), Address 0x00 Bit Bit Name Default 15 Reset 0, RW/SC Reset Initiate software Reset / Reset in Process Normal operation. This bit, which is self-clearing, returns a value of ...
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Table 8. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name Default 15 100BASE-T4 0, RO/P 14 100BASE-TX 1, RO/P Full Duplex 13 100BASE-TX 1, RO/P Half Duplex 12 10BASE-T 1, RO/P Full Duplex 11 10BASE-T 1, RO/P Half ...
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... The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83846A. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num- ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National's IEEE assigned OUI is 080017h. Table 9. PHY Identifi ...
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This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto- Negotiation. Table 11. Auto-Negotiation Advertisement Register (ANAR), address 0x04 Bit Bit Name RESERVED 13 RF 12:11 RESERVED ...
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This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful autonegotiation if Next-pages are supported. Table 12. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 Bit Bit Name ...
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Table 13. Auto-Negotiation Link Partner Ability Register (ANLPAR) Next Page, address 0x05 Bit Bit Name ACK ACK2 11 Toggle 10:0 CODE <000 0000 0000>, This register contains additional Local Device and Link Partner status ...
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This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 15. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 Bit Bit Name RESERVED ACK2 11 TOG_TX ...
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Extended Registers This register provides a single location within the register set for quick access to commonly accessed information. Table 16. PHY Status Register (PHYSTS), address 0x10 Bit Bit Name 15:14 RESERVED 13 Receive Error Latch 12 Polarity Status ...
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Table 16. PHY Status Register (PHYSTS), address 0x10 (Continued) Bit Bit Name Default 7 RESERVED Remote Fault Jabber Detect Auto-Neg Complete Loopback Status Duplex Status ...
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This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 17. False Carrier Sense Counter Register (FCSCR), address 0x14 Bit Bit Name 15:8 RESERVED 7:0 ...
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Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (Continued) Bit Bit Name Default 7 Unused 0,RO 6 RESERVED 5 FORCE_100_OK RESERVED 3 RESERVED 2 NRZI_BYPASS SCRAM_BYPASS DESCRAM_BYPA ...
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Table 21. PHY Control Register (PHYCTRL), address 0x19 Bit Bit Name Default 15:12 Unused 11 PSR_15 10 BIST_STATUS 0, RO/LL 9 BIST_START 8 BP_STRETCH 7 PAUSE_STS 6 RESERVED 1, RO/P 5 LED_CNFG Strap, RW 4:0 PHYADDR[4:0] Strap ...
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Table 22. 10Base-T Status/Control Register (10BTSCR), Address 0x1A Bit Bit Name 15:9 Unused 8 LOOPBACK_10_DIS 7 LP_DIS 6 FORCE_LINK_10 5 FORCE_POL_COR 4 POLARITY 3 AUTOPOL_DIS 2 RESERVED 1 HEARTBEAT_DIS 0 JABBER_DIS Default 0, 10Base-T Loopback Disable: This bit ...
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Table 23. CD Test Register (CDCTRL), Address 0x1B Bit Bit Name Default 15 CD_ENABLE DCDCOMP FIL_TTL RESERVED none RISETIME Strap RESERVED none FALLTIME Strap, RW ...
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Electrical Specifications Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature (T ) STG Power Dissipation (PD) Lead Temp. (TL) (Soldering, 10 sec) ESD Rating (R ...
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Symbol Pin Types Parameter R RD Differential Input INdiff Resistance V TD 100M Transmit TPTD_100 Voltage V TD 100M Transmit TPTDsym Voltage Symmetry V TD 10M Transmit TPTD_10 Voltage C I CMOS Input IN1 Capacitance SD RD 100BASE-TX THon Signal ...
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PGM Clock Timing X1 TX_CLK Parameter Description T2.0.1 TX_CLK Duty Cycle 6.3 MII Serial Management Timing MDC MDIO (output) MDC MDIO (input) Parameter Description T3.0.1 MDC to MDIO (Output) Delay Time T3.0.2 MDIO (Input) to MDC Setup Time T3.0.3 ...
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Mb/s Timing 6.4.1 100 Mb/s MII Transmit Timing TX_CLK TXD[3:0] TX_EN TX_ER Parameter Description T4.1.1 TXD[3:0], TX_EN, TX_ER Data Setup to TX_CLK T4.1.2 TXD[3:0], TX_EN, TX_ER Data Hold from TX_CLK 6.4.2 100 Mb/s MII Receive Timing T4.2.1 RX_CLK ...
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Transmit Packet Latency Timing TX_CLK TX_EN TXD TD Parameter Description T4.3.1 TX_CLK to TD Latency Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the ...
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Transmit Timing (t +1 rise TD T4.5.2 TD eye pattern Parameter Description T4.5.1 100 Mb and t R 100 Mb/s t and t Mismatch R F T4.5.2 100 Mb/s TD Transmit Jitter Note: Normal Mismatch is ...
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Receive Packet Latency Timing RD IDLE T4.6.1 CRS RXD[3:0] RX_DV RX_ER/RXD[4] Parameter Description T4.6.1 Carrier Sense ON Delay T4.6.2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the first bit of ...
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Mb/s Timing 6.5.1 10 Mb/s MII Transmit Timing TX_CLK TXD[3:0] TX_EN Parameter Description T5.1.1 TXD[3:0], TX_EN Data Setup to TX_CLK T5.1.2 TXD[3:0], TX_EN Data Hold from TX_CLK 6.5.2 10 Mb/s MII Receive Timing T5.2.1 RX_CLK RXD[3:0] RX_DV Parameter ...
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Transmit Timing (Start of Packet) TX_CLK TX_EN TXD[0] TPTD Parameter Description T5.3.1 Transmit Enable Setup Time from the Rising Edge of TX_CLK T5.3.2 Transmit Data Setup Time from the Rising Edge of TX_CLK T5.3.3 Transmit Data Hold Time ...
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Receive Timing (Start of Packet) TPRD CRS RX_CLK RXD[0] RX_DV Parameter Description T5.5.1 Carrier Sense Turn On Delay (TPRD to CRS) T5.5.2 Decoder Acquisition Time T5.5.3 Receive Data Latency T5.5.4 SFD Propagation Delay Note: 10BASE-T receive Data Latency ...
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Mb/s Heartbeat Timing TXE TXC COL Parameter Description T5.7.1 CD Heartbeat Delay T5.7.2 CD Heartbeat Duration 6.5.8 10 Mb/s Jabber Timing TXE TPTD COL Parameter Description T5.8.1 Jabber Activation Time T5.8.2 Jabber Deactivation Time 6.5.9 10BASE-T Normal Link ...
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Auto-Negotiation Fast Link Pulse (FLP) Timing T5.10.1 Fast Link Pulse(s) T5.10.4 Parameter Description T5.10.1 Clock, Data Pulse Width T5.10.2 Clock Pulse to Clock Pulse Period T5.10.3 Clock Pulse to Data Pulse Period T5.10.4 Number of Pulses in a Burst ...
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Reset Timing V CC HARDWARE RSTN MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T6.1.1 Post RESET Stabilization time prior to MDC preamble for reg- ister accesses T6.1.2 Hardware Configuration Latch- in ...
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Loopback Timing TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] Parameter Description T7.0.1 TX_EN to RX_DV Loopback Note: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” 550 s ...
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Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) H/W or S/W Reset (with PHYAD = 00000) MODE Parameter Description T8.0.1 From software clear of bit 10 in the BMCR register to the transi- ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Plastic Quad Flat Package JEDEC (LQFP) Order Number DP83846AVHG NS Package Number VHG80A 2. A critical component is any component of a life support ...