W83787F Winbond, W83787F Datasheet
W83787F
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W83787F Summary of contents
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... The W83787IF integrates a disk drive adapter ,two 16550 compatible UARTs, and one parallel port with EPP mode, ECP mode, and joystick mode. The disk drive adapter functions of the W83787IF is sames as W83787F which including a floppy disk drive controller compatible with the industry standard 765, data separator, write pre- compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic ...
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FEATURES 1.44MB Floppy Disk Controller --- Support four 360K,720K,1.2M,1.44M floppy disk drives --- Data Transfer Rate 250Kb/s,300Kb/s,500Kb/s --- Single 24Mhz crystal input --- FDD anti-virus function with software write protect and FDD write enable signal, write data signal force inactive ...
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PIN CONFIGURATION / ...
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Host Interface, continued SYMBOL PIN I/O AEN 62 I System address bus enable 63 I CPU I/O read signal IOR 64 I CPU I/O write signal IOW DRQ2 100 O When DRQ2 = 1, a DMA request is being made ...
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Serial Port Interface SYMBOL PIN I Clear To Send is the modem control input. CTSA 47 The function of these pins can be tested by reading Bit 4 of the CTSB handshake status register Data ...
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Serial Port Interface, continued SYMBOL PIN I/O 36 I/O UART A Request To Send. An active low informs the modem or data RTSA set that the controller is ready to send data. HPRTAS1 During power-on reset, this pin is pulled ...
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Game Port/Power Down Interface, continued PDCIN 3 I This input pin controls the chip power down. When this pin is active, the clock supply to the chip will be inhibited and the output pins will be tri- IRRX2 I stated ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I ACK PRINTER MODE: ACK An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O PRINTER MODE: SLCT SLCT active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I SLIN PRINTER MODE: SLIN Output line for detection of printer selection. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I AFD PRINTER MODE: AFD An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O PD0 9 I/O PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O PD2 11 I/O PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O PD4 13 I/O PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. I EXTENSION ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O PD6 16 I/O PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD ...
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IDE and FDC Interface, continued SYMBOL PIN I DBENL During normal operations, DBENL is used to enable the low byte buffer of the IDE bus. When DBENL is active, it accesses I/O O IDBEN addresses 1F0H - 1F7H ...
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IDE and FDC Interface, continued During normal operations this pin is used to select the IDE controller. 95 I/O CS1 CS1 decodes the HDC addresses 3F6H and 3F7H (376H, 377H). HADSEL During power-on reset this pin selects the HDC address ...
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IDE and FDC Interface, continued SYMBOL PIN I Step output pulses. This active low open drain output produces a STEP pulse to move the head to another track This schmitt input from the disk drive is ...
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... LPT1 (378) (Default Disabled Note: When the parallel port is disabled, the eight function modes (W83757 mode, EXTFDD mode, EXTADP mode, EXT2FDD mode, JOYSTICK mode, EPP mode, ECP mode, and ECP/EPP mode) are all inhibited. Table 1-4 : PIN W83787F/777F 1 nRESIDE 2 PDBDIR/nFDCEN 3 PDCIN 42 ...
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FDC FUNCTIONAL DESCRIPTION 2.1 W83787IF FDC The floppy disk controller of the W83787IF integrates all of the logic required for floppy disk control.The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, and FDC ...
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FDC Commands Command Symbol Descriptions: C: Cylinder number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0, step out DIR = 1, step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data ...
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Read Data PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W ...
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Read Deleted Data,Continued PHASE R Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (3) Read A Track ...
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Read ID PHASE R Command W 0 MFM Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ ...
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Write Deleted Data PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- ...
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Format A Track PHASE R Command W 0 MFM ---------------------- N ------------------------ W --------------------- SC ----------------------- W --------------------- GPL --------------------- W ---------------------- D ------------------------ Execution W ---------------------- C ------------------------ for Each W ---------------------- ...
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Specify PHASE R Command ---------SRT ----------- | --------- HUT ---------- | W |------------ HLT ----------------------------------| ND (11) Seek PHASE R Command -------------------- NCN ...
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Scan Equal PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ PHASE R -------------------- EOT ----------------------- W ...
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Scan Low or Equal PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- ...
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Scan High or Equal PHASE R Comman W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- ...
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Digital Output Register (DO Register) (Write 3F2H/372H) The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit ...
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Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. TAPE ...
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Status Register 0 (ST0) 7 1-0 4 US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected NR ...
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Status Register 3 (ST3 2.3.5 Digital Input Register (DI Register) (Read 3F7H/377H) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes PC/ only Bit 7 is checked by the BIOS. ...
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IDE The IDE interface is essentially the AT bus ported to the hard disk drive. The hard disk controller resides on the IDE hard disk drive. So the IDE interface provides only chip select signals and AT bus signals ...
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Register Address TABLE UART Register Bit Map Register Address Base 8 Receiver RBR RX Data Buffer BDLAB = 0 Bit 0 Register (Read Only) 8 Transmitter TBR TX Data Buffer Register BDLAB = 0 Bit 0 ...
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UART Control Register (UCR) (Read/Write) The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection Notes: Bit 7: BDLAB. When this ...
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TABLE WORD LENGTH DEFINITION DLS1 DLS0 DATA LENGTH 4.2.2 UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of the data transfer during communication. 7 ...
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Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit ...
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Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins Notes: Bit 7: This bit is the opposite ...
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TABLE 4-4 FIFO TRIGGER LEVEL BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode ...
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TABLE 4-5 INTERRUPT CONTROL FUNCTION ISR Bit Bit Bit Bit Interrupt Interrupt Type priority First UART Receive Status Second RBR Data Ready ...
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Programmable Baud Generator (BLL/BHL) (Read/Write) Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to generate a 1.8461 MHz frequency and divides divisor from the baud generator ...
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User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. 4.2.10 IRQ3/IRQ4 Setting IRQ3 and IRQ4 are the interrupt pins for UARTA and UARTB in the W83787IF. These two interrupt pins ...
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TABLE 5-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST PIN NUMBER CONNECTOR OF W83787I 1 19 2-9 9-14,16- Notes: n<name > : Active Low ...
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HOST PIN NUMBER CONNECTOR OF W83787I ATTRIBUTE ...
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Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data swapper. 5.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status ...
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W83757 (SPP) mode: When this bit is a logic 1, pin PRTOE is high, and PRTBEN (CR3 bit 7) is low, the parallel port is in input mode (read); when this bit is a logic 0, the parallel port is ...
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EPP data write cycle to be performed, and the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes ...
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A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 S have elapsed from the start of the EPP cycle to the time WAIT is deasserted. The current EPP cycle is aborted when a ...
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ECP Register and Mode Definitions NAME ADDRESS data Base+000h ecpAFifo Base+000h dsr Base+001h dcr Base+002h cFifo Base+400h ecpDFifo Base+400h tFifo Base+400h cnfgA Base+400h cnfgB Base+401h ecr Base+402h Note: The base addresses are 3BCH, 378H, and 278H, which are determined ...
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Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are ...
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Device Control Register (DCR) The bit definitions are as follows Notes: Bit 6, 7: These two bits are logic one during a read and cannot be written. Bit 5: This bit has no effect and the ...
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Register B) Mode = 111 The bit definitions are as follows Notes: Bit 7: This bit is read-only low level during a read. This means that this chip does not support hardware ...
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Reserved. 110 Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. 111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 ...
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Bit map of ECP port registers, continued D7 D6 ECP Data FIFO ecpDFifo tFifo Test FIFO cnfgA 0 0 cnfgB compress intrValue ecr MODE Notes: 1. These registers are available in all modes. 2. All FIFOs use one common ...
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ECP Pin descriptions, continued NAME TYPE nFault (nPeriphRequest) I nInit (nReverseRequest) O nSelectIn (ECPMode) O 5.3.13 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, ...
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FIFO Operation The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used ...
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Extension Adapter Mode (EXTADP)* In this mode, the W83787IF redefines the printer interface pins for use as an extension adapter, allowing a pocket peripheral adapter card to be installed through the DB-25 printer connector. The pin assignments for the ...
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Joystick Mode* The joystick mode allows users to plug a joystick into the parallel port DB-25 connector. The pin definitions are shown in Table 5- Pins NSTB AFD NSLIN and INIT output high as a voltage ...
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Configuration Register 0 (CR0), EFER = 89H, EFIR = 0H When EFER is loaded with 89H and EFIR with 0H, the CR0 register can be accessed through EFDR. The bit definitions for CR0 are as follows Notes: ...
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PRTMOD1 PRTMOD0 (Bit 3, Bit 2): These two bits and PRTMOD2 (CR9 bit7) determine the parallel port mode of the W83787IF (see Table 7-1 on next page ). Table 7-1 PRTMODS2 PRTMOD1 (BIT 7 OF CR9) (BIT 3 OF CR0) ...
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SINA and SINB in idle state No register read or write to chip If all of these conditions are met, a counter begins to count down. While the timer is counting down, the W83787IF remains in normal operating mode, and ...
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Configuration Register 1 (CR1) EFER = 89H, EFIR = 1H When 89H is loaded into EFER and 01H is loaded into EFIR, the CR1 register can be accessed through EFDR. The bit definitions are as follows Notes: ...
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ABCHG (Bit 7): This bit enables the FDC AB Change Mode. (The default value depends on DBENL /ABCHG at power-on setting. If there is no setting, the default is normal mode.) 0 Drives A and B assigned as usual 1 ...
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Examples (debug instructions): Example 7.6: Enable IDE, FDC; enable extension adapter mode (assume I/O port is 300H 250 251 252 58 (Set Extension Adapter Mode 251 02 (XRD and XWR ...
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GMODS (Bit 4): This bit selects the adapter mode or portable mode. 0 Selects the portable mode. Pins 41 and 39 will function as PFDCEN and PEXTEN 1 Selects the adapter mode. Pins 41 and 39 will function as GMRD ...
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PRTTRI (Bit 3): This bit enables or disables the tri-state outputs of parallel port in power-down mode. 0 The output pins of the parallel port will not be tri-stated when parallel port is in power- down mode. 1 The output ...
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Bit 7: Reserved OSCS2 (Bit 6): This bit and OSCS1, OSCS0 (bit CR0) select one of the W83787IF's power-down functions. Refer to descriptions of CR0. SEL4FDD (Bit 5): Selects four FDD mode 0 Selects two ...
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FDCPWD (Bit 3): This bit controls the power to the FDC. 0 Power is supplied to the FDC. 1 Puts the FDC in power-down mode. IDEPWD (Bit 2): This bit controls the power of the IDE. 0 Power is supplied ...
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Three mode FDD select (EN3MODE = 1): 01 RWC = 0, selects 1.2 MB high-density FDD. 10 RWC = 1, selects 1.44 MB high-density FDD. 11 Don't care RWC, selects 720 KB double-density FDD. FDD C type 1,0 (Bit 5,4): ...
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Once this bit is set high, the FDC operates normally, but because pin WE is inactive, the FDD will not write data to diskettes. For example diskette is formatted with DISFDDWR = 1, after the format command has ...
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Configuration Register 9 (CR9) EFER = 89H, EFIR = 09H When 89H is loaded into EFER and 09H is loaded into EFIR, the CR9 register can be accessed through EFDR. The bit definitions are as follows Notes: ...
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Configuration Register A (CRA) EFER = 89H, EFIR = 0AH When 89H is loaded into EFER and 0AH is loaded into EFIR, the CRA register can be accessed through EFDR. The bit definitions are as follows Notes: ...
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PEXTECP (Bit 1): This bit controls whether the PEXTEN pin is active in ECP mode. 0 PEXTEN is not active in ECP mode 1 PEXTEN is active in ECP mode PEXTECPP (Bit 0): This bit controls whether the PEXTEN pin ...
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URIRSEL (Bit 3): This bit select UART B operating in normal function function. 0 Select UART B as Infrared function. 1 Select UART B as normal function. During power-on reset, the default value is set by Pin ...
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SIRRX1, SIRRX0 (Bit 5, 4): These two bits select IRRX in the IR function. 00 IRRX2 (Pin 3, PDCIN) 01 IRRX1 (Pin 42, SINB) 10 IRRX4 (Pin 94, nCS0) 11 IRRX3 (Pin 1, nRESIDE) During the power-on reset, the default ...
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Configuration Register E, F (CR0E, CR0F) EFER = 89H, EFIR = 0EH, 0FH Bit 7~ Bit 0: Reserved for testing. 7.2.16 Configuration Register 10H (CR10) EFER = 89H, EFIR = 10H (R/W) When 89H is loaded into EFER and ...
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GIO0ADR10~8 (Bit 2 ~ Bit0): These 3 bits select GIO0 address bit 10 ~ bit 8, another GIO0 address bit 7 ~ bit 0 are defined in CR10 bit 7 ~ bit 0. 7.2.18 Configuration Register 12H (CR12) EFER = ...
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GIO1 ADR MODE1 ~ Bit 5 ~ Bit 3: Reserved. GIO1ADR10~8 (Bit 2 ~ Bit0): These 3 bits select GIO1 address bit 10 ~ bit 8, another GIO1 address bit 7 ~ bit 0 are ...
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GIOP0M GIOP0MD1 Data outport port (SD0 When (AEN=L) & (IOR =L) & (SA10~0=GIO0AD10~0), the value of SD0 will present at GIOP0 0 10 Data input port (SD0 When (AEN=L) & (IOR =L) & (SA10~0=GIO0AD10~0), the ...
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GCS0IOR GCS0IOW 0 0 The GIOP0 functions as a Chip select pin, and will active when (AEN=L) & (SA10~0 = GIOAD10~ The GIOP0 functions as a Chip select pin, and will active when (AEN=L) & (SA10~0 = GIOAD10~0) ...
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Notes: GIOP1MD2~0 (Bit 7 ~ Bit 5): These three bits define GIOP1 pin mode, that is either Chip-Select or Data Port, as shown in following table. GIOP1M GIOP1MD1 Data outport port (SDP0 ...
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GCS1IOR, GCS1IOW (Bit 3, Bit2): These two bits define GIO1 Chip Select Active Mode, that is in IOR , or IOW , or IOR / IOW , as shown in the following table. GCS1IOR GCS1IOW ...
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Bit Map Configuration Registers Table 7-6 Power-on Reg. Reset Value D7 (D7-D0) CR0 sss1 ss00 IDEEN HADSEL CR1 00ss ssss ABCHG CR2 0000 0000 RA9 RA8 CR3 0011 0000 PRTBEN GMENL CR4 0000 0000 PRTPWD GMPWD CR5 0000 0000 ...
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DC CHARACTERISTICS ( 5 0V PARAMETER SYM. Input Low Voltage V IL Input High Voltage V IH Input Leakage Current I LIH Input Leakage Current I ...
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AC Characteristics 8.3.1 FDC: Data rate = 500Kb/300Kb/250Kb/sec PARAMETER SYM. T SA9-SA0, AEN, DACK , AR CS, setup time to IOR ¡õ SA9-SA0, AEN, DACK , hold time for IOR ¡ô T IOR width RR Data access ...
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AC Characteristics, FDC continued PARAMETER SYM. T IOW or IOR response time MRW from DRQ TC width T TC RESET width T RST T INDEX width IDX T DIR setup time to STEP DST T STD DIR hold time ...
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UART/Parallel Port PARAMETER Delay from Stop to Set Interrupt Delay from IOR Reset Interrupt Delay from Initial IRQ Reset to Transmit Start Delay from to Reset interrupt Delay from Initial IOW to interrupt Delay from Stop to Set Interrupt ...
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Parallel Port Mode Parameters PARAMETER PD0-7, INDEX , STROBE, AUTOFD Delay from IOW IRQ Delay from ACK , nFAULT IRQ Delay from IOW IRQ Active Low in ECP and EPP Modes ERROR Active to IRQ Active 8.3.6 EPP Data ...
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EPP Data or Address Read Cycle Timing Parameters, continued PARAMETER PBDIR Set to Command PD Hi-Z to Command Asserted WAIT Asserted to Command Asserted WAIT Deasserted to Command Deasserted Time out PD Valid to WAIT Deasserted PD Hi-Z to ...
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EPP Data or Address Write Cycle Timing Parameters, continued PARAMETER Time out Command Deasserted to WAIT Asserted IOW Deasserted to WRITE Deasserted and PD invalid 8.3.8 Parallel Port FIFO Timing Parameters PARAMETER DATA Valid to nSTROBE Active nSTROBE Active ...
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IrDA Receive Timing Parameters PARAMETER Pulse Width at 115.2k baud Pulse Width at 57600 baud Pulse Width at 38400 baud Pulse Width at 19200 baud Pulse Width at 9600 baud Pulse Width at 4800 baud Pulse Width at 2400 ...
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Amplitude Shift Keyed IR (ASK-IR) Receiver Timing Parameters PARAMETER Modulated Output Bit Time Off Bit Time Modulated Output ON Modulated Output OFF Modulated Output ON Modulated Output OFF 8.9.14 Amplitude Shift Keyed IR (ASK-IR) Transmit Timing Parameters PARAMETER Modulated ...
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TIMING WAVEFORMS 9.1 FDC Processor Read Operation SA0-SA9 AEN CS TAR DACK TRR IOR TFD D0-D7 IRQ Processor Write Operation SA0-SA9 AEN TAW DACK IOW D0-D7 IRQ DMA Operation TAM DRQ DACK TMA IOW or IOR TMW(IOW) TMR(IOR) WD ...
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IDE SA<0:9> IOR IOW DATA READ IDED7 D7 DATA WRITE IDED7 T3 D7 CS0 CS1 T1 IOCS16 DBENL DBENH 9.3 UART/Parallel SIN (RECEIVER STAR INPUT DATA) IRQ3 or IRQ4 IOR (READ RECEIVER BUFFER REGISTER) SERIAL OUT STAR (SOUT) THRS ...
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Modem Control Timing IOW (WRITE MCR) RTS,DTR ¢x CTS,DSR ¢x DCD ¢x ¢ ¡ ö ¡ ÷ ¢x ¢ ¢x IRQ3 or ¢x IRQ4 ¢x ¢ IOR (READ MSR) RI ¢x ¢x ¢x ¢ ACK ¢x ¡ ÷ ¢x ...
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Parallel Port 9.4.1 Parallel Port Timing IOW INIT,STROBE AUTOFD, SLCTIN PD<0:7> ACK t2 IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ Publication ReleaseDate:Sep 1995 - 98 - W83787IF Revision A1 ...
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EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 ADDRSTB t24 DATASTB WAIT t18 t19 t25 ...
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EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY t9 t10 t11 WRITE t13 PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR t15 t16 t17 t18 t19 t21 t20 Publication ...
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EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 ADDRSTB t24 DATASTB WAIT t18 t19 t25 ...
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EPP Data or Address Write Cycle (EPP Version 1.7) A10-A0 SD<0:7> t1 IOW IOCHRDY t9 t10 t11 WRITE t13 PD<0:7> DATAST ADDRSTB WAIT 9.4.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t15 t16 ...
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ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE t5 BUSY 9.4.8 ECP Parallel Port Reverse Timing PD<0:7> t1 nACK t5 nAUTOFD Publication ReleaseDate:Sep 1995 - 103 - W83787IF t3 ...
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Extension Adapter Mode Command Cycle IOR IOW XRD XWR tx1 SA<0:2> XA<0:2> tx2 XD<0:7> 9.4.10 Extension Adapter Mode Interrupt Cycle XIRQ IRQ7 9.4.11 Extension Adapter Mode DMA Cycle XDRQ tx6 DRQX DACKX XDACK TC XTC tx3 tx5 tx7 tx8 ...
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IrDA Receiver Timing 0 SINB IRRXn IRRXn Note: 1. IRRXn: CR0C.bit0 (TX2INV active high (default). IRRXn: CR0C.bit0 (TX2INV active low. 9.4.13 IrDA Transmit Timing SOUTB IRTXn ...
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Amplitude Shift Keyed IR (ASK-IR) Receiver Timing SINB IRRXn IRRXn T3 500KHZ T5 500KHZ Notes: 1: Receive 500KHZ Pulse Detection Criteria: A received pulse is detected if the received pulse is minimum of 0.8 s. ...
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APPLICATION CIRCUITS 10.1 Parallel Port Extension FDD JP13 13 WE2/SLCT 25 12 WD2/ MOB2/BUSY 23 10 DSB2/ACK 22 9 PD7 21 8 PD6 20 7 PD5 19 6 DCH2/PD4 18 RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 ...
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Parallel Port Extension 2FDD JP13 13 WE2/SLCT 25 12 WD2/PE 24 MOB2/BUSY DSB2/ACK 22 9 DSA2/PD7 21 8 MOA2/PD6 20 7 PD5 19 6 DCH2/PD4 18 RDD2/PD3 5 STEP2/SLIN 17 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 ...
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Four FDD Mode W83777F DSA DSB MOA MOB 11.0 PACKAGE DIMENSIONS (100-pin QFP 100 See Detail F y Seating Plane 74LS139 ...
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... Differences between W83877 and W83787IF eature rief W83877: W83777F + Dummy Plug and Play + IR W83787IF: W83787F + IR D escription Illustrates the pins that have different functionality on the W83787F, W83787IF and the W83877F. The following table lists the pins that differ. Pin W83787F/777F 1 nRESIDE 2 PDBDIR/nFDCEN 3 ...
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... Pin W83787F/777F 98 nDACK2 IRQ6 99 100 DRQ2 A description of the functional differences for each pin follows. W83787IF: Pin 1: If the nRESIDE is not used, the alternate functions can be used for serial infrared receive input. Select IRRX3 by setting bits 5:4 in CR0D to be 10. Pin 2: In CARD features this pin is not used, so can be used for IRTX2. Set bits 6:7 in CR0D to 00 (that is default setting) ...
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... UART B as normal function. The default value of URIRSEL is dependent on pin 92 at power on setting bit 2: GIOSEL = 0 select the IDE pins definition compatible to W83787F IDE pins definition. =1 select the W83787IF IDE pins definition and general purpose I/O function. The default value of GIOSEL is dependent on pin 91 at power on setting. ...
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CR0D bit 7: SIRTX1 => IRTX pin selection bit 1 bit 6: SIRTX0 => IRTX pin selection bit 0 SIRTX1 SIRTX0 IRTX output on pin bit 5: SIRRX1 => IRRX pin selection ...
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CR11: bit 3 - bit 0: GIO0AD10 - GIO0AD8 => GIOP0 (pin 92) address bit 10 - bit 8 bit 5- bit 3 : Reversed bit 7 - bit 6: G0CADM1 - G0CADM0 => GIOP0 address bit compare mode selection ...
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X bit 4: GIO0CSH =0 the Chip Select pin will active LOW when (AEN=L) AND (SA10-0 = GIO0AD10-0) OR (NIOR=L) OR (NIOW=L) =1 the Chip Select pin will active HIGH when (AEN=L) AND (SA10-0 = GIO0AD10-0) OR (NIOR=L) OR ...
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X bit 4: GIO1CSH =0 the Chip Select pin will active LOW when (AEN=L) AND (SA10-0 = GIOAD10-0) OR (NIOR=L) OR (NIOW=L) =1 the Chip Select pin will active HIGH when (AEN=L) AND (SA10-0 = ...
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B. W83877F Configuration Register CR0D ~ CR15 Same as W83787IF CR1E This register is used to select the base address of Game Chip Select Decoder (GAMECS) from 100H - 3F0H on 16-byte boundries. The default value is 81H. NCS=0 and ...
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CR22 This register is used to select the base address of the IDE Interface Alternate Status Register from 106H - 3F6H on 16-byte boundries + 6. The default value is FDH. NCS=0 and A10=0 are required to access the IDE ...
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CR26 This register is used to select DMA resources for the FDC (bits and the parallel port (bits 3 - 0). Any unselected DMA is in tristate. The default value is 23H. bit 7- bit4, bit 3 ...
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... C. Loopback test IR function: 1-1. First, you must configure the configuration registers of 787IF which you can use the program supplied by Winbond such as W787I.EXE. How to use the program W787I.EXE? You should be in the DOS prompt and type W787I command then it show a config IR's draft. In the row of URIRSEL, you select IR function ...
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... Short the terminal of IRTX and IRRX, then use the program TIR.EXE supplied by Winbond. 2-2. Also you can use DEBUG.EXE command in DOS prompt. The commands are shown as follows: -O 2fb 80 -O 2f8 0c // Set Baud rate 9600bps -O 2f9 00 -O 2fb 03 *** Test IR function *** - I 2f8 // Clear the data buffer - I 2fd // The return value must be 60, if not, you must execute " ...
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Configuration Register of IR (CR0C) (B).Set IR Pin Assignment (CR0D) (A).Set Low Baud Rate (2400 bps) (B).Sequence output data 0~255 and (A).Set Mid. Baud Rate (19200 bps) (B). Test method is same as 2400 bps. (A).Set the highest Baud ...
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Command usage DOS prompt, type SELFTIR <IRTX> <IRRX> 2. Put on the IR module or short the terminal of IRTX and IRRX Press any key to continue. Example: Use Pin94 and Pin95 as IRTX and IRRX respectively, then ...