CXD2498R Sony, CXD2498R Datasheet
CXD2498R
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CXD2498R Summary of contents
Page 1
... Timing Generator for Frame Readout CCD Image Sensor Description The CXD2498R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX282 CCD image sensor. Features • Base oscillation frequency 45MHz • Electronic shutter function • Supports various drive modes such as draft and AF mode • ...
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... SSI 31 SCK 32 SEN 33 SSGSL 6 RST 2 TEST1 27 TEST2 Pulse Generator 1/2 Latch Register SSG – 2 – CXD2498R PBLK 21 CLPDM 22 OBCLP 23 ADCLK ID/EXP 5 WEN 40 V1A 42 V1B V1C V3A 46 V3B ...
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... V3B 46 V3C 47 SUB Groups of pins enclosed in the figure indicate sections for which power supply separation is possible – 3 – CXD2498R ADCLK 22 OBCLP 21 CLPDM 20 PBLK XSHD 19 18 XSHP ...
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... High: Normal operation, Low: Reset control High: CKI sync, Low: MCKO sync With pull-down resistor High: Internal SSG valid, Low: External sync valid With pull-down resistor With pull-down resistor With pull-down resistor – 4 – CXD2498R Schmitt trigger input Schmitt trigger input ...
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... CCD vertical register clock output –7.5V power supply. (Power supply for vertical driver) — 46 V3B O CCD vertical register clock output. 47 V3C CCD vertical register clock output SUB CCD electronic shutter pulse output. O Description – 5 – CXD2498R Schmitt trigger input Schmitt trigger input ...
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... OL6 OL Feed current where I = –2.4mA OH7 OH Pull-in current where I = 4.8mA OL7 OL V1A/B/C, V2, V3A/B/ –8.25V V1A/B/C, V2, V3A/B/ –0.25V V1A/B/C, V3A/B/C = 0.25V V1A/B/C, V3A/B/C = 14.75V SUB = –8.25V SUB = 14.75V – 6 – CXD2498R Min. Typ. Max. Unit 3.0 3.3 3.6 V 3.0 3.3 3.6 V 3.0 3.3 3 ...
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... To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. (Within the recommended operating conditions) Conditions LVth fmax = 50MHz sine wave IN Conditions – 7 – CXD2498R Min. Typ. Max. Unit 0.3V ...
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... Switching Waveforms V1A (V1B, V1C, V3A, V3B, V3C) V2 (V4) SUB Waveform Noise VCLH TTMH TTHM 90% 90% TTLM 10% 10% 90% 90% 10% TTLM 90% 90% 10% TTLH TTHL 90% 90% 10% VCMH VCML VCLL – 8 – CXD2498R VH TTML VM 10% VL TTML ...
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... Serial interface data CXD2498R C3: 820pF C4: 8pF C5: 320pF – 9 – CXD2498R CKI ...
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... DD 0. ts1 th1 c ts3 0. ts2 (Within the recommended operating conditions) Definition Enlarged view c th1 (Within the recommended operating conditions) Definition – 10 – CXD2498R Min. Typ. Max. Unit Example: During frame mode 0. Min. Typ. Max. Unit ...
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... Restriction with an operating frequency of 22.5MHz. Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD2498R at the timing shown in “Serial interface clock internal loading characteristics (1)” above. However, one exception to this is when the data such as STB is loaded to the CXD2498R and controlled at the rising edge of SEN. See ”Description of Operation”. ...
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... Definition 0. ts1 th1 0. (Within the recommended operating conditions) Definition 0. ts1 0.8V DD (Within the recommended operating conditions) Definition – 12 – CXD2498R c DD Min. Typ. Max. Unit Min. Typ. Max. Unit 0.2V d ...
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... Output variation characteristics MCKO WEN, ID/EXP WEN and ID/EXP load capacitance = 10pF Symbol t Time until the above outputs change after the rise of MCKO pd1 0. tpd1 (Within the recommended operating conditions) Definition – 13 – CXD2498R Min. Typ. Max. Unit ...
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... Description of Operation Pulses output from the CXD2498R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin Symbol CAM SLP No ...
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... Serial Interface Control The CXD2498R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B/C and V3A/B/C, etc. take the ternary value. ...
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... OFF 1 OFF — — See D16 to D17 PTMD. — — ID See D34 to D35 PTOB. See D36 to D37 LDAD. See D38 to D39 STB. — — – 16 – CXD2498R Data = 1 RST All Enabled 0 Disabled All 0 All 0 0 — — ...
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... SPL specification D41 D42 to — D47 Function Data = 0 10000001 Other values See D08 to D09 CTG. See D10 to D19 SVD. See D20 to D31 SHD. See D32 to D41 SPL. — – 17 – CXD2498R Data = 1 RST Enabled All 0 Disabled All 0 All 0 All 0 All 0 — 0 ...
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... Control data: D38 to D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD2498R and control is applied immediately at the rising edge of SEN. D39 D38 Symbol Operating mode X 0 CAM Normal operating mode ...
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... Control data: [Drive mode] The CXD2498R realizes various drive modes by using control data D10 to D11 MODE and D16 to D17 PTMD. The drive mode bits are loaded to the CXD2498R and reflected at the falling edge of VD. These details are described below. First, the basic drive mode is assigned using the control data D10 to D11 MODE. ...
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... SPL Vertical period specification for high-speed shutter operation (000h Note) The bit data definition area is assured in terms of the CXD2498R functions, and does not assure the CCD characteristics. The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure time calculation formula is shown below ...
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... Incidentally, SPL is counted as “000h”, “001h”, “002h” and conformance with SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa. SVD 1 002h 10Fh SPL 001 SVD SHD 1 001h 002h 10Fh – 21 – CXD2498R 1 000h 050h 002 1 000h 000h 0A3h ...
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... The transition point is midpoint value (1515ck) of the last SUB pulse falling edge and each V1A/ B/C and V3A/B/C ternary output falling edge. When there is no SUB pulse, the later ternary output falling edge (1590ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation – 22 – CXD2498R 0 1 ...
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Chart-1 Vertical Direction Timing Chart VD 1013 1017 1 HD SUB C High-speed sweep block V1A V1B V1C V2 V3A V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The number of SUB pulses is determined by the serial ...
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Chart-2 Vertical Direction Timing Chart VD 1038 1 HD SUB C High-speed sweep block V1A V1B V1C V2 V3A V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The number of SUB pulses is determined by the serial interface ...
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Chart-3 Vertical Direction Timing Chart VD 519 527 1 HD SUB H High-speed sweep block V1A V1B V1C V2 V3A V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The number of SUB pulses is determined by the serial ...
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Chart-4 Vertical Direction Timing Chart VD 249 SUB J V1A V1B V1C V2 V3A V3B V3C CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The ...
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Chart-5 Vertical Direction Timing Chart VD 530 1 HD SUB C High-speed sweep block V1A V1B V1C V2 V3A V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The number of SUB pulses is determined by the serial interface ...
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Chart-6 Vertical Direction Timing Chart VD 302 1 HD SUB C High-speed sweep block V1A V1B V1C V2 V3A V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The number of SUB pulses is determined by the serial interface ...
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Chart-7 Vertical Direction Timing Chart VD 519 1 HD SUB C High-speed sweep block V1A V1B V1C V2 V3A V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The number of SUB pulses is determined by the serial interface ...
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Chart-8 Vertical Direction Timing Chart VD 295 1 HD SUB C High-speed sweep block V1A V1B V1C V2 V3A V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The number of SUB pulses is determined by the serial interface ...
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Chart-9 Vertical Direction Timing Chart VD 125 1 HD SUB High-speed sweep block M J V1A V1B V1C V2 V3A V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The number of SUB pulses is determined by the serial ...
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Chart-10 Vertical Direction Timing Chart SUB M High-speed sweep block V1A V1B V1C V2 V3A V3B V3C V4 CCD OUT PBLK OBCLP CLPDM ID/EXP WEN The number of SUB pulses is determined by the serial interface ...
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... WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... V4 Logic alignment portion The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... V3C V4 The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... V3C V4 The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... V3C V4 The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. ...
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... RG XSHP XSHD HD’ indicates the HD which is the actual CXD2498R load timing. The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. The logical phase of ADCLK can be specified by the serial interface data. MODE ...
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... This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD2498R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data are not the same. ...
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... This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD2498R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data are not the same. ...
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... SUB pin of the CCD image sensor from going to negative potential. t1 20% 20 Digital OUT CDS/ADC Block CXD2498R SSG V- VCO – 50 – CXD2498R ID/EXP 4 WEN 5 CKO 25 MCKO Signal Processor 30 Block RST 3 SNCSL 6 SSGSL Controller 15.0V 0V –7.5V ...
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... M 0.1 ± 0.1 NOTE: Dimension “ ” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-48P-L01 LQFP048-P-0707 LEAD MATERIAL PACKAGE MASS – 51 – CXD2498R B + 0.05 0.127 – 0.02 0.1 S 0.18 ± 0.03 DETAIL B:PALLADIUM EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g Sony Corporation ...