P28F002BC-T120 Intel Corporation, P28F002BC-T120 Datasheet
P28F002BC-T120
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P28F002BC-T120 Summary of contents
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X 8) BOOT BLOCK FLASH MEMORY n High Performance Read 80/120 ns Max Access Time 40 ns Max. Output Enable Time n Low Power Consumption 20 mA Typical Read Current n x8-Only Input/Output Architecture Space-Constrained 8-bit Applications ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT © INTEL CORPORATION, 1996 CG-041493 ...
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INTRODUCTION .............................................5 1.1 Designing for Density Upgradeability............5 1.2 Main Features ..............................................5 1.3 Applications..................................................6 1.4 Pinouts.........................................................7 1.5 Pin Descriptions .........................................10 2.0 PRODUCT DESCRIPTION............................11 2.1 Memory Organization .................................12 2.1.1 Blocking...............................................12 2.1.2 28F002BC-T Block Memory Map.........12 3.0 PRINCIPLES OF OPERATION .....................12 3.1 ...
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BOOT BLOCK FLASH MEMORY REVISION HISTORY Number -001 Original version -002 Pin 2 of 44-Lead PSOP changed from Alternate program command (10H) removed WSM transition table added -003 40-Lead PDIP package added 4 Item PRELIMINARY ...
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INTRODUCTION This datasheet comprises the specifications for the 28F002BC 2-Mbit flash memory. Section 1 provides an overview of the 2-Mbit flash memory, including applications, pinouts, and descriptions. Section 2 describes the memory organization in detail. Section 3 defines a ...
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BOOT BLOCK FLASH MEMORY Host Bus Main Memory Pentium® Processor 82430FX PCIset 100/90 MHz (82437FX) Cache Figure 1. 28F002BC-T Interface to a Pentium® Microprocessor System I , the maximum program current mA. The PP V voltage ...
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Reprogrammable systems, such as computers, are ideal applications 28F002BC. Portable and hand-held computer applications are becoming more complex with the addition of power management software to take advantage of the latest microprocessor technology, the availability of ROM-based application software, pen ...
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... GND Figure 3. The 40-Lead PDIP Offers the Lowest Cost Package Solution P28F002BC 4 BOOT BLOCK 40-LEAD PDIP RP WE ...
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WP ...
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BOOT BLOCK FLASH MEMORY 1.5 Pin Descriptions Table 1. 28F002BC Pin Descriptions Symbol Type ADDRESS INPUTS for memory addresses. Addresses are internally latched A , INPUT –1 during a write cycle – TSOP and ...
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PRODUCT DESCRIPTION Output Buffer Power Reduction Control Input Buffer Y-Decoder Address X-Decoder Latch Address Counter Figure 5. 28F002BC Internal Block Diagram PRELIMINARY 28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY DQ - Input Buffer Identifier ...
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BOOT BLOCK FLASH MEMORY 2.1 Memory Organization 2.1.1 BLOCKING The 28F002BC features an asymmetrically-blocked architecture that provides system integration. Each block can be erased up to 100,000 times. The block sizes have been chosen to optimize their functionality ...
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CUI. The purpose of the Write State Machine (WSM automate the write and erasure of the device completely. The WSM will begin operation upon receipt of a signal from the ...
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BOOT BLOCK FLASH MEMORY 3.2.2 INTELLIGENT IDENTIFIERS The manufacturer and device codes are read via the CUI or by taking the A pin Writing 90H the CUI places the device into Intelligent ...
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Table 4. Command Bus Definitions Command Notes Read Array Intelligent Identifier 1,2 Read Status Register Clear Status Register Program Setup Block Erase/Confirm Erase Suspend/Resume ADDRESS BA = Block Address SRD = Status Register Data IA = Identifier Address IID = ...
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BOOT BLOCK FLASH MEMORY Read Status Register (70H) This is one of three commands that is executable while the WSM is operating. After this command is written, a read of the device will output the contents of the ...
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Erase Resume (D0H) This command will cause the CUI to clear the Suspend state and clear the WSM Status Bit to a “0,” but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect ...
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BOOT BLOCK FLASH MEMORY Table 5. Status Register Bit Definition WSMS ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS Erase Suspended ...
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When the status register indicates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. If the erase operation was unsuccessful, bit 5 of the status register will be set (within 1.5 ...
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BOOT BLOCK FLASH MEMORY Start Write 40H and Byte Address Write Data and Data Address Read Status Register No SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Start Write 20H and Block Address Write D0H and Block Address Read Status Register Suspend Erase Loop No 0 Yes Suspend SR.7 = Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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BOOT BLOCK FLASH MEMORY Start Write B0H Read Status Register 0 SR Erase Completed SR Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Erase Resumed Read Array Data ...
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Power Consumption 3.5.1 ACTIVE POWER With CE logic-low level and RP logic- high level, the device is placed in the active mode. The device I current is a maximum ...
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BOOT BLOCK FLASH MEMORY 3.7 Power Supply Decoupling Flash memory’s power switching characteristics require careful device decoupling methods. System designers should consider three supply current issues: 1. Standby current levels (I ) CCS 2. Active current levels (I ...
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ELECTRICAL SPECIFICATIONS 4.1 Absolute Maximum Ratings Operating Temperature During Read ................................ 0°C to +70°C During Write and Block Erase...... 0°C to +70°C Temperature Bias .................... –10°C to +80°C Storage Temperature................... –65°C to +125°C Voltage on Any Pin (except V ...
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BOOT BLOCK FLASH MEMORY 4.2.1 CAPACITANCE Symbol Parameter C Input Capacitance IN C Output Capacitance OUT NOTES: 1. Sampled, not 100% tested. 2. For the 28F002BC, address pin A follows the C 10 4.2.2 INPUT/OUTPUT TEST CONDITIONS 2.4 ...
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DC CHARACTERISTICS Table 7. DC Characteristics Symbol Parameter Notes I Input Load Current IL I Output Leakage Current Standby Current CCS CC V Deep Power-Down I CC CCD Current V Read Current I CC CCR I ...
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BOOT BLOCK FLASH MEMORY Table 7. DC Characteristics (Continued) Symbol Parameter Notes I RP# Boot Block Unlock RP# Current A Intelligent Identifier Current A Intelligent Identifier Voltage V Input Low Voltage IL ...
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AC CHARACTERISTICS Table 8. AC Characteristics: Read Only Operations Symbol Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# to Output Delay PHQV t OE# to Output Delay ...
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BOOT BLOCK FLASH MEMORY Device and Address Selection V IH ADDRESSES (A) Address Stable CE# ( OE# ( WE# ( High Z ...
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Table 9. AC Characteristics: WE#—Controlled Write Operations Symbol Parameter t WE# Pulse Width High WHWL t Duration of Programming Operation WHQV1 t Duration of Erase Operation (Boot) WHQV2 t Duration of Erase Operation WHQV3 (Parameter) t Duration of Erase Operation ...
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BOOT BLOCK FLASH MEMORY ADDRESSES ( AVAV IH CE# ( ELWL V IH OE# ( WHWL V IH WE# ( ...
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Table 10. AC Characteristics: CE#—Controlled Write Operations Symbol Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going PHEL Low t WE# Setup to CE# Going Low WLEL t Boot Block Lock Setup to CE# Going PHHEH ...
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BOOT BLOCK FLASH MEMORY ADDRESSES ( AVAV IH WE# ( WLEL V IH OE# ( EHEL V IH CE# ( ...
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... Product Line Designator for all Intel Flash products Density/Organization 00X = x8-only ( VALID COMBINATIONS: 40-Lead TSOP 40-Lead PDIP Commercial 2 M E28F002BC-T80 P28F002BC-T80 E28F002BC-T120 P28F002BC-T120 PRELIMINARY 28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY APPENDIX 44-Lead PSOP PA28F002BC-T80 PA28F002BC-T120 Access Speed (ns) 80, 120 ...
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BOOT BLOCK FLASH MEMORY WSM TRANSITION TABLE Write State Machine Current/Next States Current SR.7 Data Read Program State When Array Setup Read (FFH) (40H) Read Read Program Array “1” Array Array Setup Program Setup “1” Status * Program ...
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ADDITIONAL INFORMATION RELATED INTEL INFORMATION Order Number 292130 AB-57 Boot Block Architecture for Safe Firmware Updates 292098 AP-363 Extended Flash BIOS Concepts for Portable Computers 292148 AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM 292161 AP-608 ...