MT90869 Zarlink Semiconductor, MT90869 Datasheet
MT90869
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MT90869 Summary of contents
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... Flexible 16 K Digital Switch (F16kDX) Ordering Information MT90869AG MT90869AG2 *Pb Free Tin/Silver/Copper *Note: the package thickness is different than the MT90869AG (see drawing at the end of the data sheet). • Local port accepts 32 ST-BUS streams with data rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s, in any combination • ...
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... Per stream subrate switching at 4 bit, 2 bit and 1 bit depending on stream data rate Applications • Central Office Switches (Class 5) • Mediation Switches • Class-independent switches • Access Concentrators • Scalable TDM-Based Architectures • Digital Loop Carriers MT90869 2 Zarlink Semiconductor Inc. Data Sheet ...
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... The microprocessor may monitor channel data in the backplane and local data memories. The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port. The MT90869 is manufactured body, 1.27 mm ball-pitch, 272-PBGA to JEDEC standard MS- 034 BAL-2 Iss. A. ...
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... Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.0 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.1 Test Access Port (TAP 11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.2.2.1 The Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.2.2.2 The Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 MT90869 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Input Bit Rate Registers (LIBRR0-31 13.12.2 Local Output Bit Rate Resisters (LOBRR0-31 13.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.13.1 Backplane Input Bit Rate Registers (BIBRR0-31 13.13.2 Backplane Output Bit Rate Registers (BOBRR0-31 13.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.15 Revision Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 MT90869 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - MT90869 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - MT90869 PBGA Connections (272 PBGA) Pin Diagram (as viewed through top of package Figure 3 - 8,192 x 8,192 Channels (16 Mb/s), Bidirectional Switching Figure 4 - 16,384 x 16,384 Channels (16 Mb/s), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure Blocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6 - Local Port Timing Diagram for 2,4,8 and 16 Mb/s stream rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7 - Backplane Port Timing Diagram for and 32 Mb/s stream rates ...
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... Table 44 - Output Bit Rate (LOBR) Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 45 - Backplane Input Bit Rate Register (BIBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 46 - Backplane Input Bit Rate (BIBR) Programming Table Table 47 - Backplane Output Bit Rate Register (BOBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 48 - Backplane Output Bit Rate (BOBRR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 MT90869 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 49 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 50 - Revision Control Register (RCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 MT90869 List of Tables 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Item 2, Backplane Frame Pulse Setup Time before C8i clock falling edge Item 3, Backplane Frame Pulse Hold Time 72 from C8i clock falling edge MT90869 Item The internal frame boundary alignment description is changed from the clock rising or falling edge to rising edge only. Also added description to specify setting the C8IPOL bit in the Control Register to one for clock rising edge alignment operation ...
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... Figure 26, ST-BUS Local Timing Diagram 79 (16 Mb/s) Figure 27, ST-BUS Local Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) 80 MT90869 Changed C8i frame boundary active edge from falling to rising edge. Changed C8i frame boundary active edge from falling to rising edge. Changed C8i frame boundary active edge from falling to rising edge ...
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... BST D15 D12 D8 i23 i24 i25 i30 Y BST BST IC BST D14 D11 VDD_ i26 i27 i31 CORE A1 corner identified by metalized marking. Figure 2 - MT90869 PBGA Connections (272 PBGA) Pin Diagram MT90869 A11 A14 DS ODE DTA TCK A7 A10 IC CS ...
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... N2, P1, P2, P3, P4, R1 BSTi16 - 31 R2, R3, T1, T2, T3, T4, U1,W1, W2, W3, Y1, Y2, U5, V4, W4, Y4 MT90869 Description Power Supply for Periphery Circuits: +3.3 V Power Supply for Core Logic Circuits: +1.8 V Power Supply for Analogue PLL: +1.8 V Ground Backplane Serial Input Streams Tolerant, Internal pull-down). In Non-32 Mb/s Mode, these pins accept serial TDM data streams at a data-rate of:- 16 ...
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... E3, E4, F1, F2, F3, G1, G2, G3, G4, H1, H2, H3, J1, J2, J3, J4 BCSTo0-3 C14, A15, B15, C15 MT90869 Description Backplane Serial Output Streams Tolerant, Three-state Outputs). In Non-32 Mb/s Mode, these pins output serial TDM data streams at a data-rate of:- 16.384 Mb/s (with 256 channels per stream), 8 ...
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... TRST B14 RESET C12 MT90869 Description Frame Pulse Input (5 V Tolerant). This pin accepts the Frame Pulse signal. The pulse width may be active for 122 ns or 244 ns at the frame boundary and the Frame Pulse Width bit (FPW) of the Control Register must be set Low (default) for a 122 ns and set High for a the 244 ns pulse condition ...
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... H18, H19, H20, J17, J18, J19, J20, K17, K18 LCSTo0-3 C17, C16, B16, A16 MT90869 Description Local Serial Input Streams Tolerant with internal pull-down). These pins accept serial TDM data streams at a data-rate of:- 16.384 Mb/s (with 256 channels per stream), 8 ...
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... U2, U3, V2, V3, V11, V12, V15, V16, W10, W11, W15, W16, W17, W20, Y3, Y10, Y15, Y16 MT90869 Description Output Drive Enable (5 V Tolerant, Internal pull-up). An asynchronous input providing Output Enable control to the BSTo0- 31, LSTo0- 31, BCSTo0-3 and LCSTo0-3 outputs. When LOW, the BSTo0-31 and LSTo0- 31 outputs are driven high or high impedance (dependent on the BORS and LORS pin settings respectively) and the outputs BCSTo0-3 and LCSTo0-3 are driven low ...
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... Backplane input to Local output switching. Often a system design does not need to differentiate between a Backplane and Local side, and merely needs maximum switching capacity. In this case, the MT90869 can be used as shown in Figure 4 to give the full 16,384 x 16,384 channel capacity. ...
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... BSTi0-31 LSTi0-15 BSTo0-31 LSTo0-15 Total 48 streams input and 48 output Figure Blocking Configuration MT90869 MT90869 Total 16 streams input and 16 streams output 18 Zarlink Semiconductor Inc. ...
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... Figure 6, Local Port Timing Diagram for 2,4,8 and 16 Mb/s stream rates. 2.2.1.1 Local Input Port The bit rate for each input stream is selected by writing to a dedicated Local Input Bit Rate Register (LIBRR0-31). Refer to Local Input Bit Rate Register (LIBRRn) Bits. MT90869 19 Zarlink Semiconductor Inc. Data Sheet ...
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... LSTi/LSTo0- Mb/s) ST LSTi/LSTo0- Mb/s) GCI Figure 6 - Local Port Timing Diagram for 2,4,8 and 16 Mb/s stream rates MT90869 Rate Selection Capability (for each individual stream) 2.048, 4.096, 8.192 or 16.384 Mb/s - Non-32 Mb/s Mode 32.768 Mb Mb/s Mode 2.048, 4.096, 8.192 or 16.384 Mb/s - Non-32 Mb/s Mode Unused - 32 Mb/s Mode 2.048, 4.096, 8.192 or 16.384 Mb/s - Non-32 Mb/s Mode 32 ...
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... High-impedance state controlled by the BE bit of the Backplane Connection Memory. The data source (i.e., from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane Connection Memory. Refer to Section 6.2, Backplane Connection Memory and Section 12.4, Backplane Connection Memory Bit Definition. MT90869 21 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Port Timing Diagram for 2,4,8 and 16 Mb/s stream rates, and Figure 7, Backplane Port Timing Diagram for and 32 Mb/s stream rates. The MT90869 will automatically detect whether an ST-BUS or a GCI-BUS style frame pulse is being used for the master frame pulse (FP8i). The device will detect the frame boundary alignment using the rising edge of the input clock (C8i), provided the C8IPOL bit in Table 16, “ ...
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... Backplane Frame Pulse Input and Local Frame Pulse Output Alignment The MT90869 accepts a Backplane Frame Pulse (FP8i) and generates the Local Frame Pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant three frame delay for data being switched. ...
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... The local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR31, corresponding to the local data streams, LSTi0 to LSTi31, and the backplane input delay is defined by the Backplane Input Delay registers, BIDR0 to BIDR31, which correspond to the backplane data streams, BSTi0 to BSTi31. MT90869 ...
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... BSTi0-31/LSTi0- Bit Delay = 1 Ch254 BSTi0-31/LSTi0- Bit Delay = 7 1/2 Ch254 BSTi0-31/LSTi0- Bit Delay = 7 3/4 Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mb/s MT90869 Ch0 Bit Delay, 1/4 Ch0 ...
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... The backplane output advancement registers, BOAR0-31 are used to control the backplane output advancement. The advancement is determined with reference to the internal system clock rate (131.072 MHz). For 2 Mb/s, 4 Mb/ Mb/s streams the advancement may cycles, -4 cycles or -6 cycles, which converts to MT90869 Ch0 1 ...
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... The input pin, LORS, selects whether the Local output streams, LSTo0-31 are set to high impedance at the output of the MT90869 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-3 signals. Setting LORS to a LOW state will configure the output streams, LSTo0-31, to transmit bi-state channel data with per- channel high-impedance determined by external circuits under the control of the LCSTo0-3 outputs ...
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... The Local Output Enable Bit (LE) of the Local Connection Memory has direct per-channel control on the high- impedance state of the Local Output streams, LSTo0-31. Programming a LOW state will set the stream output of the MT90869 to High Impedance for the duration of the channel period. See Section 12.3, Local Connection Memory Bit Definition, for programming details. ...
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... Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams MT90869 Channel No Mb/s 4 Mb/s 2 Mb/s Mb 3-2 3 ...
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... Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams Note 1: Clock Period count is referenced to Frame Boundary. Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream. Note 3-1 to 3-4: See Section 4.1.1 for examples of Channel Control Bit for streams of different data-rates. MT90869 Channel No Mb/s ...
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... The input pin, BORS, selects whether the Backplane output streams, BSTo0-31 are set to high impedance at the output of the MT90869 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the BCSTo0-3 signals ...
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... The state of the BORS pin is detected and the MT90869 configured accordingly during a RESET operation, e.g. following power-up. The BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. 4.2.1 BORS Set LOW, Non-32 Mb/s Mode The data (channel control bit) transmitted by BCSTo0-3 replicates the Backplane Output Enable Bit (BE) of the Backplane Connection Memory, with a LOW state indicating the channel to be set to High Impedance ...
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... Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams (Non-32 Mb/s Mode) MT90869 Channel No ...
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... Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams (Non-32 Mb/s Mode) Note 1: Clock Period count is referenced to Frame Boundary. Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream. Note 3-1 to 3-4: See Section 4.2.1 for examples of Channel Control Bit for streams of different data-rates. MT90869 Channel No. BCSTo2 BCSTo3 16 Mb/s 8 Mb/s ...
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... The data (channel control bit) transmitted by BCSTo0-3 replicates the Backplane Output Enable Bit (BE) of the Backplane Connection Memory, with a LOW state indicating the channel be set to High Impedance. See Section 12.4, Backplane Connection Memory Bit Definition for setting the Backplane Output Enable Bit (BE). MT90869 4 3 ...
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... BCSTo0, BCSTo1, BCSTo2 and BCSTo3. C16o BCSTo0 1 Period 2039 0 2040 4 2041 8 2042 12 3-1 2043 0 2044 4 2045 8 3-2 2046 12 2047 0 Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32 Mb/s Mode) MT90869 Allocated Stream No. BCSTo1 BCSTo2 BCSTo3 ...
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... Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32 Mb/s Mode) MT90869 Channel No. BCSTo2 BCSTo3 32 Mb ...
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... Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32 Mb/s Mode) Note 1: Clock Period count is referenced to Frame Boundary. Note 2: The Channel Numbers presented relate to the specific stream operating at a data-rate of 32.768Mb/s. Note 3-1 to 3-4: See Section 4.2.2 for examples of Channel Control Bits. MT90869 Channel No. BCSTo2 BCSTo3 ...
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... Backplane Output streams, BSTo0-31 (for Non-32 Mb/s Mode) and BSTo0-15 (for 32 Mb/s Mode). Programming a LOW state will set the stream output of the MT90869 to High Impedance for the duration of the channel period. See Section 12.4, Backplane Connection Memory Bit Definition, for programming details ...
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... Each data memory location corresponds to an input stream and channel number. To provide constant delay and maintain frame integrity, the MT90869 utilizes four pages of data memory. Consecutive frames are written in turn to each page of memory. Reading is controlled to allow a channel data written in frame read during frame N+3 ...
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... Connection Memory Description The MT90869 incorporates two connection memories, Local Connection Memory and Backplane Connection Memory. 6.1 Local Connection Memory The Local Connection Memory (LCM) is 16-bit wide with 8,192 memory locations to support the Local output port. The most significant bit of each word, bit [15], selects the source stream from either the Backplane or the Local port and determines the Backplane-to-Local or Local-to-Local data routing ...
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... DTA handshake when accessed but any data read from the bus will be invalid. There must be a minimum between CPU accesses, to allow the MT90869 device to recognize the accesses as separate (i.e., a minimum must separate the de-assertion of DTA (to high) and the assertion of CS and/ initiate the next access) ...
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... The RESET pin must remain low for two input clock cycles (C8i) to guarantee a synchronized reset release. When a RESET is applied to the MT90869, the CS line is inhibited and the DTA line may become active through simultaneous microport activity. External gating of the DTA line with CS is recommended to avoid bus conflict in applications incorporating multiple devices with individual reset conditions ...
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... Start Ch=0 Length=256 0 Start Ch=0 Length=3 0 Start Ch=254 Length=4 Channels containing PRBS sequence Note: Length = Start Chan. + No. of Consecutive channels Once Started BER transmission continues until stopped by the BER control register:- FP stream Figure 17 - Examples of BER transmission channels MT90869 ...... ..... ..... ..... 254 ...... ..... ...
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... TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled to V when not driven from an external source. 11.2 TAP Registers The MT90869 uses the public instructions defined in the IEEE 1149.1 standard with the provision of an Instruction Register and three Test Data Registers. 11.2.1 Test Instruction Register The JTAG interface contains a four-bit instruction register ...
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... The Bypass Register The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo. 11.2.2.3 The Device Identification Register The JTAG device ID for the MT90869 is 0086914B Version, Bits <31:28>:0000 Part No., Bits <27:12>:0000 1000 0110 1001 Manufacturer ID, Bits <11:1>:0001 0100 101 Header, Bit < ...
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... LE Local Output Enable Bit When LOW the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the LORS pin. When HIGH the channel is active. MT90869 Description Description Set to a default value of 0 Local Data Memory ...
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... Bit BSRC selects the switch configuration for Local-to-Backplane or Backplane-to-Backplane. When the per- channel Message Mode is selected (BMM = HIGH), the lower byte of the BCM word (BCAB7-0) will be transmitted as data on the output stream (BSTo0-31) in place of data defined by the Source Control, Stream Address and Channel Address bits. MT90869 Description Description 48 Zarlink Semiconductor Inc ...
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... BCAB8-0 Source Channel Address Bits. The binary value of these 9 bits represents the input channel number when BMM is LOW. BCAB7-0 are transmitted as data when BMM is set HIGH in Message Mode. Table 14 - BCM Bits for Backplane-to-Backplane Switching (32Mb/s mode) MT90869 Description Mode) Description 49 Zarlink Semiconductor Inc ...
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... Backplane Input Bit rate Register 0, BIBRR0 - Register 31, BIBRR31 012D 014C Backplane Output Bit rate Register 0, BOBRR0 - Register 31, BOBRR31 014D Memory BIST Register, MBISTR H 3FFF Revision control register, RCR H Table 15 - Address Map for Register (A14 = 0) MT90869 Register 50 Zarlink Semiconductor Inc. Data Sheet ...
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... When LOW, the BSTo0-31 and LSTo0-31 are driven high or high impedance, dependent on the BORS and LORS pin settings respectively, and BCSTo0-3 and LCSTo0-3 are driven low. When HIGH, the BSTo0-31, LSTo0-31, BCSTo0-3 and LCSTo0-3 are enabled. MT90869 Description ODE Pin OSB bit ...
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... Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 18 - Frame Boundary Conditions, ST- BUS Operation MT90869 Description Table 16 - Control Register Bits Frame Boundary 52 Zarlink Semiconductor Inc. Data Sheet ...
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... Memory Block Programming feature is activated. When the MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM. Bits 12-0 of the BCM are set LOW. MT90869 Frame Boundary Description 53 Zarlink Semiconductor Inc ...
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... SBERTXB 0 6 PRBSB 0 Table 18 - Bit Error Rate Test Control Register (BERCR) Bits MT90869 Description Description Reserved. Backplane Lock (READ ONLY). This bit is automatically set HIGH when the receiver has locked to the incoming data sequence. The bit is reset by a LOW to HIGH transition on SBERRXB ...
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... Reserved 7-0 LCD(7:0) Table 19 - Local Channel Delay Register (LCDRn) Bits MT90869 Description Local Lock (READ ONLY). This bit is automatically set HIGH when the receiver has locked to the incoming data sequence. The bit is reset by a LOW to HIGH transition on SBERRXL PBER Reset for Local. ...
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... The data rate can be either 2 Mb/s, 4 Mb/ Mb/s. The LIDR0 to LIDR31 registers are configured as follows: LIDRn Bit Name (where 31) 15-5 Reserved 4-0 LIDn(4:0) Table 21 - Local Channel Delay Register (LIDRn) Bits MT90869 Corresponding Delay Bits Input Stream LCD7-LCD0 0000 0000 1 Channel 0000 0001 2 Channels 0000 0010 3 Channels ...
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... Table 22 - Local Input Bit Delay Programming Table MT90869 1 / bit period Corresponding Delay Bits LID3 LID2 ...
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... Channels 3 Channels 4 Channels 5 Channels ... ... 509 Channels 510 Channels 511 Channels Table 24 - Backplane Input Channel Delay (BCD) Programming Table MT90869 Name Reset Reserved 0 Reserved BCD(8:0) 0 Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the backplane input stream ...
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... Table 26 - Backplane Input Bit Delay Programming Table MT90869 Name Reset Reserved 0 Reserved BID(4:0) 0 Backplane Input Bit Delay Register The binary value of these bits refers to the input bit delay value for the backplane input stream Corresponding Delay Bits ...
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... LSTo0 to LSTo31. The possible adjustment is - cycles of the internal system clock (131.072 MHz). The LOAR0 to LOAR31 registers are configured as follows: LOARn Bit Name (where 31) 15-2 Reserved 1-0 LOA(1:0) Table 27 - Local Output Advancement Register (LOARn) Bits MT90869 Corresponding Delay Bits BID4 BID3 BID2 ...
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... Backplane Output Advancement For 2 Mb/s, 4 Mb/s, 8 Mb/s & 16 Mb/s clock Rate 131.072 MHz 0 (Default) -2 cycle -4 cycles -6 cycles Table 30 - Backplane Output Advancement (BOAR) Programming Table MT90869 Corresponding Advancement Bits LOA1 Name Reset ...
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... Local Transmit BER Length Bits The binary value of these bits define the number of channels in addition to the Start Channel that the BER data will be transmitted on. (i.e., Total Channels = Start Channel + LTXBL value) Table 32 - Local BER Length Register (LTXBLR) Bits MT90869 Reset 0 Reserved. 0 Local BER Send Stream Address Bits. ...
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... Name Reset 15-0 LBC(15:0) 0 Table 35 - Local BER Count Register (LBCR) Bits MT90869 Description Reserved. Local Receive BER Length Bits The binary value of these bits define the number of channels in addition to the Start Channel allocated for the BER receiver. (i.e., Total Channels = Start Channel + LRXBL value) Description Reserved ...
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... Reserved 0 8-0 BRXBL(8:0) 0 Table 38 - Backplane Receive BER Length (BRXBLR) Bits MT90869 Reserved. Backplane BER Send Stream Address Bits The binary value of these bits define the backplane output stream to transmit the BER data. Backplane BER Send Channel Address Bits The binary value of these bits define the backplane output Start Channel in which the BER data is transmitted ...
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... Reserved 1-0 LIBR(1:0) Table 41 - Local Input Bit Rate Register (LIBRRn) Bits MT90869 Description Reserved. Backplane BER Receive Stream Address Bits The binary value of these bits defines the backplane input stream that receives the BER data. Backplane BER Receive Channel Address Bits The binary value of these bits define the backplane input start channel in which the BER data will be received ...
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... Mb/s and backplane streams 16-31 will be unused. The BIBRR registers are configured as follows: BIBRn Bit Name ( for n=0 to 31) 15-2 Reserved 1-0 BIBR(1:0) Table 45 - Backplane Input Bit Rate Register (BIBRRn) Bits MT90869 LIBR0 Bit rate for stream Mb Mb ...
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... The Memory BIST register enables the built-in-self-test function for the on-chip memory testing. Two consecutive write operations are required to start MBIST. The first with only Bit 12 (LV_TM) set High (i.e., 1000h), the second with Bit 12 maintained High but with the required start bit(s) set High. MT90869 BIBR0 Bit rate for stream n ...
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... High indicates completion of Memory BIST sequence. 0 BISTPCL 0 Local Connection Memory Pass/Fail Bit (Read only). This bit indicates the Pass/Fail status following completion of the Memory BIST sequence. A HIGH indicates Pass, a LOW indicates Fail. Table 49 - Memory BIST Register (MBISTR) Bits MT90869 Description 68 Zarlink Semiconductor Inc. Data Sheet ...
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... The revision control register stores the binary value of the silicon revision number. This register is read only. The RCR register is configured as follows: Bit Name Reset Value 15-4 Reserved 3-0 RC(3:0) defined by silicon Table 50 - Revision Control Register (RCR) Bits MT90869 0 Reserved. Revision Control Bits 69 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Operating Temperature 2 Positive Supply 3 Positive Supply 4 Positive Supply 5 Input Voltage 6 Input Voltage Tolerant Inputs Voltages are with respect to ground (V ) unless otherwise stated. SS MT90869 Symbol Min. V -0.5 DD_CORE V -0.5 DD_IO V -0.5 DD_PLL V -0 -0.5 I_5V ...
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... Output Pin Capacitance T S Voltages are with respect to ground (V ) unless otherwise stated Electrical Characteristics Timing Parameter Measurement: Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low MT90869 Sym. Min. Typ. Max DD_Core I 160 200 DD_Core I 100 DD_IO ...
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... Falling edge to Local Frame Boundary 19 FP16o Output Delay from Local Frame Boundary to Rising edge 20 C16o Clock Period 21 C16o Clock Pulse Width High 22 C16o Clock Pulse Width Low 23 C16o Clock Rise/Fall Time MT90869 Sym. Min. Typ. t 210 244 BFPW244 t 10 122 BFPW122 ...
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... CK_int * FP8o (244ns) t FODF8_244 FP8o (122 ns) t LCH8 C8o FP16o t FODF16 t t LCH16 LCL16 C16o * CK_int is the internal clock signal of 131.072MHz Figure 20 - Backplane and Local Clock Timing Diagram for ST-BUS MT90869 t BFPW244 t BFPH244 t BFPW122 t BFPH122 t BCL8 BCP8 t fBC8i t LFBOS t LFPW8_244 t FODR8_244 ...
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... FP8i C8i CK_int* FP8o t LCL8 C8o FP16o t FRS16o t t LCH16 LCL16 C16o * CK_int is the internal clock signal of 131.072 MHz Figure 21 - Backplane and Local Clock Timing for GCI-BUS MT90869 t BGFPW t t BGFPS BGFPH t BCP8 t t BCL8 BCH8 t t fBC8i t LFBOS t GFPW8 t t GFPS8o ...
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... Bit0 4.096 Mb/s Ch63 BSTo0 - 31 Bit0 4.096 Mb/s Ch63 BSTi0 - 31 Bit0 2.048 Mb/s Ch31 BSTo0 - 31 Bit0 2.048 Mb/s Ch31 * CK_int is the internal clock signal of 131.072 MHz Figure 22 - ST-BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) MT90869 Sym. Min BIDS32 41 t BIDS16 87 t BIDS8 178 t BIDS4 361 t ...
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... Mb/s BSTo0 - 15 Bit1 Bit1 32.768 Mb/s Ch511 Ch511 BSTi0 - 31 Bit1 16.384 Mb/s Ch255 BSTo0 - 31 Bit0 Ch255 16.384 Mb/s * CK_int is the internal clock signal of 131.072 MHz Figure 23 - ST-BUS Backplane Data Timing Diagram (32 Mb/s, 16 Mb/s) MT90869 t BIDS32 t BSIS32 t BSIH32 BSOD32 Bit7 Bit6 Bit5 Bit0 Ch0 ...
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... Bit7 Ch63 4.096 Mb/s BSTo0 - 31 Bit7 Ch63 4.096 Mb/s BSTi0 - 31 Bit7 Ch31 2.048 Mb/s Bit7 BSTo0 - 31 Ch31 2.048 Mb/s * CK_int is the internal clock signal of 131.072 MHz Figure 24 - GCI BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) MT90869 t BIDS8 t BSIS8 t BSIH8 BSOD8 Bit1 Bit2 Bit3 Ch0 ...
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... Figure 25 - GCI BUS Backplane Data Timing Diagram (32 Mb/s, 16 Mb/s) Local Clock Data Timing Characteristic 1 Local Frame Boundary Offset 2 Input data sampling point 3 Local Serial Input Set-up Time 4 Local Serial Input Hold Time 5 Local Serial Output Delay MT90869 t BIDS32 t BSIS32 t BSIH32 BSOD32 ...
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... FP8i C8i CK_int * LSTi0 - 31 Bit1 Bit0 Ch255 16.384 Mb/s Ch255 LSTo0 - 31 Bit0 Ch255 16.384 Mb/s * CK_int is the internal clock signal of 131.072 MHz Figure 26 - ST-BUS Local Timing Diagram (16 Mb/s) MT90869 t LFBOS t LIDS16 t LSIS16 t LSIH16 Bit7 Bit6 Ch0 Ch0 t LSOD16 Bit7 Bit6 Ch0 Ch0 79 Zarlink Semiconductor Inc. ...
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... Figure 27 - ST-BUS Local Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) Backplane and Local Output High-Impedance Timing Characteristic 1 STo delay - Active to High-Z - High-Z to Active 2 Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to High-Impedance Note 1: High Impedance is measured by pulling to mid-rail with R MT90869 t LFBOS t LIDS8 t LSIS8 t LSIH8 ...
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... Data setup on write 10 Data hold on write 11 Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory 12 Acknowledgment Hold Time Note1: High impedance is measured by pulling to the appropriate rail with R time taken to discharge MT90869 VTT t DZ Valid Data HiZ t ZD Valid Data HiZ t t ODE ODZ ...
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... DTA Figure 30 - Motorola Non-Multiplexed Bus Timing Note: There must be a minimum between CPU accesses, to allow the MT90869 device to recognize the accesses as separate (i.e., a minimum must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS (to initiate the next access). ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes: ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...