ISPLSI1024 Lattice Semiconductor Corp., ISPLSI1024 Datasheet
ISPLSI1024
Specifications of ISPLSI1024
Available stocks
Related parts for ISPLSI1024
ISPLSI1024 Summary of contents
Page 1
... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
Page 2
Functional Block Diagram Figure 1.ispLSI 1024 Functional Block Diagram RESET Generic Logic Blocks (GLBs) I I/O 1 I I I I/O 9 I/O ...
Page 3
Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
Page 4
Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure 2) Test Condition R1 A ...
Page 5
External Timing Parameters 5 2 TEST PARAMETER # DESCRIPTION COND Data Propagation Delay, 4PT bypass, ORP bypass pd1 Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max ...
Page 6
Internal Timing Parameters 2 PARAMETER DESCRIPTION # Inputs t iobp I/O Register Bypass 20 t I/O Latch Delay iolat 21 t iosu 22 I/O Register Setup Time before Clock t ioh 23 I/O Register Hold Time after Clock t ioco ...
Page 7
Internal Timing Parameters 2 PARAMETER DESCRIPTION # Outputs t ob Output Buffer Delay 47 t I/O Cell OE to Output Enabled oen 48 t odis 49 I/O Cell OE to Output Disabled Clocks t gy0 Clock Delay Global ...
Page 8
Timing Model I/O Cell Ded. In #26 I/O Reg Bypass I/O Pin #20 (Input) Input Register D Q RST #55 # 30, 31, 32 Reset Y1,2 Derivations of su, h and co from ...
Page 9
Maximum GRP Delay vs GLB Loads Power Consumption Power consumption in the ispLSI 1024 device depends on two primary factors: the speed at which the device is operating, and the number of Product ...
Page 10
Pin Description PLCC and JLCC PIN NUMBERS NAME I I/O 3 22, 23, 24, 25, I I/O 7 26, 27, 28, 29, I I/O 11 30, 32, 33, 31, I I/O 15 ...
Page 11
Pin Configuration ispLSI 1024 68-Pin PLCC Pinout Diagram I/O 43 I/O 44 I/O 45 I VCC GND ispEN RESET 1 SDI/IN 0 I/O 0 I/O 1 I/O 2 I Pins ...
Page 12
Pin Configuration ispLSI 1024 68-Pin JLCC Pinout Diagram I/O 43 I/O 44 I/O 45 I VCC GND ispEN RESET 1 SDI/IN 0 I/O 0 I/O 1 I/O 2 I Pins ...
Page 13
Part Number Description ispLSI Device Family ispLSI Device Number Speed MHz max MHz max MHz max Ordering Information f Family max (MHz ispLSI 80 60 ...