HMP8170 Intersil Corporation, HMP8170 Datasheet
HMP8170
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HMP8170 Summary of contents
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... Data Sheet NTSC/PAL Video Encoder The HMP8170 NTSC and PAL encoder is designed for use in systems requiring the generation of high-quality NTSC and PAL video. YCbCr digital video data drive the P0-P15 inputs. The Y data is optionally lowpass filtered to 6MHz and drives the Y analog output ...
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... Functional Block Diagram 2 HMP8170 ...
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... YCbCr digital video input data and generate analog video output signals. The four outputs are two composite video signals and Y/C (S-Video). The HMP8170 accepts pixel data in one of several formats and transforms it into 4:4:4 sampled luminance and chrominance (YCbCr) data. The encoder then interpolates the YCbCr data to twice the pixel rate and low pass filters it to match the bandwidth of the video output format ...
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... The format of the SAV and EAV codes are shown in Table 3. The BT.656 input may also include ancillary data to load the VBI or RTCI data registers. The HMP8170 will use the ancillary data when enabled in the VBI data input and Timing I/O registers. The ancillary data formats and the enable registers are described later in this data sheet ...
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... Start Active Video End Active Video P3 - P0: Protection bits; Ignored Video Timing Control The pixel input data and the output video timing of the HMP8170 are 59.94 fields per second interlaced. The timing is controlled by the BLANK, HSYNC, VSYNC, FIELD, and CLK2 pins. HSYNC, VSYNC, and Field Timing The leading edge of HSYNC indicates the beginning of a horizontal sync interval ...
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... BLANK is asserted. There may be an additional 0-3 CLK2 delays in modes which use CLK. The data pipeline delay through the HMP8170 is 26 CLK2 cycles. In operating modes which use CLK to gate the inputs into the encoder, the delay may be an additional 0-7 CLK2 cycles ...
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... Figure 7. At this point, the HMP8170 also scales the Y data to generate the proper output levels for the various video standards. The HMP8170 lowpass filters the Cb and Cr data to 1.3MHz prior to modulation. The lowpass filtering removes any ...
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... FREQUENCY (MHz) FIGURE 8A. FULL SPECTRUM Color Subcarrier Generation The HMP8170 uses a numerically controlled oscillator (NCO) clocked by CLK2 and a sine look up ROM to generate the color subcarrier. As shown in Figure 9, the phase increment value (PHINC) of the NCO may come from the encoder’s internal look up table, BT.656 ancillary data control register ...
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... If the registers are not updated, the encoder resends the previously loaded values. The HMP8170 provides a write status bit for each captioning line. The encoder clears the write status bit to ‘0’ when captioning is enabled and both bytes of the captioning data register have been written. The encoder sets the write status bit to ‘ ...
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... The HMP8170 provides a write status bit for each WSS line. The encoder clears the write status bit to ‘0’ when WSS is enabled and all bytes of the WSS data register have been written. The encoder sets the write status bit to ‘ ...
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... IRE for a logic 0. All transitions between levels are controlled to have a raised-cosine shape with a rise or fall time of 200ns. The HMP8170 generates teletext output on any scan line that includes teletext data in that line’s BT.656 ancillary data. The encoder must receive the ancillary data before the SAV sequence in order to output the teletext data ...
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... HPLL ep# Increment ep# (4 Nibbles) ep# ep# FSCPLL ep# Increment ep# (8 Nibbles) ep# ep# CRC P14# NOTES: The even parity (EP and EP#) bits are ignored. HPLL, PSW, F2, and F1 are ignored Don’t Care. 12 HMP8170 P14 P13 P12 P11 ...
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... The analog RGB outputs have a range of 0.3-1.0V with an optional blanking pedestal. Composite sync information (0.0-0.3V) may be optionally added to the green output. VBI data is not included on the RGB outputs. The HMP8170 also generates composite video when in RGB output mode. All four outputs are time aligned. ...
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... Host Interfaces Reset The HMP8170 resets to its default operating mode on power up, when the reset pin is asserted for at least four CLK cycles, or when the software reset bit of the host control register is set. During the reset cycle, the encoder returns its internal registers to their reset state and deactivates the I interface ...
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... BIT NUMBER FUNCTION 7-5 Input Format 000 = 16-bit 4:2:2 YCbCr 001 = 8-bit 4:2:2 YCbCr 010 = 8-bit BT.656 011 = Reserved 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved Reserved 15 HMP8170 A DATA A DATA A P REGISTER POINTED OPTIONAL FRAME TO BY MAY BE REPEATED SUBADDR n TIMES A S DATA ...
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... Active low (low during vertical sync) Polarity 1 = Active high (high during vertical sync) 0 FIELD 0 = Active low (low during odd fields) Polarity 1 = Active high (high during odd fields) 16 HMP8170 TABLE 17. VIDEO PROCESSING REGISTER SUB ADDRESS = 03 H DESCRIPTION TABLE 18. TIMING I/O REGISTER #1 SUB ADDRESS = 04 H DESCRIPTION ...
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... Setting this bit enables BT.656 ancillary data to be written into the WSS line 283 data registers. BT.656 Enable It is ignored unless in the BT.656 input mode Ignore BT.656 ancillary data 1 = Use BT.656 ancillary data 3-0 Reserved 17 HMP8170 TABLE 19. TIMING I/O REGISTER #2 SUB ADDRESS = 05 H DESCRIPTION 2 C interface PHINC register TABLE 20. AUXILIARY DATA ENABLE REGISTER ...
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... This register is cascaded with the closed caption_21A data register and they are read out MSB Data serially as 16 bits during line 18, 21 line 21 captioning is enabled. Bit D0 of the 21A data register is shifted out first. 18 HMP8170 TABLE 22. HOST CONTROL REGISTER 1 SUB ADDRESS = 0E H DESCRIPTION TABLE 23 ...
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... Reserved 5-0 Line 20 This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled WSS CRC Data ignored during PAL WSS operation. Bit D0 is shifted out first. 19 HMP8170 SUB ADDRESS = 12 H DESCRIPTION SUB ADDRESS = 13 H DESCRIPTION TABLE 28. WSS_20A DATA REGISTER ...
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... The leading edge of VSYNC at the start of an odd field is count 000 follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is configured as an output. 20 HMP8170 TABLE 33. CRC_283 REGISTER SUB ADDRESS = 19 H DESCRIPTION TABLE 34 ...
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... Field Detect This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Window Size High Size value. This bit is ignored unless HSYNC and VSYNC are configured as inputs. 21 HMP8170 TABLE 38. START V_BLANK HIGH REGISTER SUB ADDRESS = 24 H DESCRIPTION TABLE 39 ...
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... PHINC value is the phase increment value of the color subcarrier generation NCO. When the BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to determine the last PHINC value loaded via the selected interface. 22 HMP8170 TABLE 42. PHASE INCREMENT REGISTER 0 SUB ADDRESS = 6B H DESCRIPTION TABLE 43 ...
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... INPUT/ NAME NUMBER OUTPUT P0-P15 58, 55-43, 38 32-27, 23, 22 RESV 21 FIELD 34 HSYNC 35 VSYNC 36 BLANK 33 23 HMP8170 HMP8170 (PQFP) TOP VIEW Pixel input pins ...
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... COMP 2 63 VAA GND 24 HMP8170 I/O 1x pixel clock input/output input, this clock must be free-running and synchronous to the clock signal on the CLK2 pin output, this pin may drive a maximum of one LS TTL load. CLK is generated by dividing CLK2 by two or four, depending on the mode. If not driven, the circuit for this pin should include a 4-12kΩ ...
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... DC PARAMETERS, ANALOG OUTPUTS DAC Resolution Integral Nonlinearity, INL Differential Nonlinearity, DNL Output Current Output Impedance Output Capacitance Output Compliance Range 25 HMP8170 Thermal Information Thermal Resistance (Typical, Note 3) + 0.5V) PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AA Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 Maximum Storage Temperature Range . . . . . . . . . -65 Vapor Phase Soldering, 1 Minute . . . . . . . . . . . . . . . . . . . . . .220 ...
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... PSRR = 20 x log (∆V /∆ OUT 7. If using an external voltage reference not powered down. The internal voltage reference is powered down. 26 HMP8170 = 25 A TEST CONDITION (Note 4) VREF Unconnected, RSET = 133Ω VREF = 1.230V (Figure 27), RSET = 140Ω Pin not connected, using internal reference Pin connected to external reference shown in Figure 27 ...
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... Wfm ---> PEDESTAL -30.0 NOISE LEVEL = -79.9dB RMS -35.0 -40.0 -45.0 -50.0 -55.0 -60.0 -65.0 -70.0 -75.0 -80.0 -85.0 -90.0 -95.0 -100.0 1.0 2.0 3.0 AVERAGE (MHz) FIGURE 12. NOISE SPECTRUM (NTSC) 27 HMP8170 APL = 44.3% 4.0 5.0 SETUP 7.5% FIGURE 13. NTSC COLOR BAR VECTOR SCOPE PLOT FIGURE 14. NTSC FCC COLOR BAR SYSTEM LINE ANGLE (DEG) 0.0 GAIN x1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE ...
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... AVERAGE FIGURE 15. LUMINANCE NON LINEARITY (NTSC) LINE JITTER (LINE 20 TO 250) FIGURE 17. H SYNC JITTER IN A FRAME (NTSC) AVERAGE FIGURE 19. NOISE SPECTRUM (PAL) 28 HMP8170 (Continued) wfm ---> 5 STEP PEAK-TO-PEAK = 2.1 LINE FREQUENCY ERROR 100.0 99.8 -0.4 LINE FREQUENCY 15.734 (kHz) FIELD FREQUENCY 59.94 (Hz) ...
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... AVERAGE FIGURE 22. LUMINANCE NON LINEARITY (PAL) 29 HMP8170 (Continued) FIGURE 21. COLORBAR (PAL) wfm ---> 5 STEP PEAK-TO-PEAK = 1.4 LINE FREQUENCY ERROR 100.0 99.8 -0.4 LINE FREQUENCY 15.625 (kHz) FIELD FREQUENCY 50.00 (Hz) AVERAGE OFF 4TH 5TH Wfm ---> COLOR BAR 0.00 (%) -0.2 0.0 0.2 (%) FIGURE 23. LINE FREQUENCY (PAL) ...
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... GND pins should short as possible. Component Placement The optimum layout places the HMP8170 at the edge of the PCB and as close as possible to the video output connector. External components should be positioned as close as possible to the appropriate pin, ideally such that traces can be connected point to point. Chip capacitors are recommended where possible, with radial lead ceramic capacitors the second-best choice ...
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... AA External Reference Voltage If an external reference voltage is used, its circuitry should receive power from the same plane as the HMP8170. The external VREF must also be stable and well decoupled from the power plane. An example VREF circuit using a band gap reference diode is shown in Figure 27. ...
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... HMP8170 Analog Output Filters The various video standards specify the frequency response of the video signal. The HMP8170 uses 2X oversampling DACs to simplify the reconstruction filter required. Example 1.235V post filters are shown in Figure 28. The analog output filters should be as close as possible to the HMP8170. ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 33 HMP8170 Q64.14x14 64 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL ...