MB91F356B Fujitsu, MB91F356B Datasheet
MB91F356B
Related parts for MB91F356B
MB91F356B Summary of contents
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... Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store in- structions PACKAGE license Purchase of Fujitsu components conveys a license under the Philips I provided that the system conforms to the I 176-pin plastic LQFP (FPT-176P-M02 Patent Rights to use, these components Standard Specification as defined by Philips ...
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... Output compare module: 8 channels. Input capture module: 4 channels • 16-bit PPG timer 6 channels 7. UART • UART Full duplex double buffer 5 channel • Selectable parity On/Off • Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable 2 MB91F355A MB91F356B 512 KB 256 240 ...
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Internal timer for dedicated baud rate • External clock can be used as transfer clock • Assorted error detection functions (for parity, frame, and overrun errors) • 115 Kbps support 8. SIO • 3 channels for 8-bit data ...
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MB91350A Series PIN ASSIGNMENT PG5/SCK5 133 NMI 134 X1A 135 V 136 SS X0A 137 MD2 138 MD1 139 MD0 140 X0 141 V 142 CC X1 143 INIT 144 V 145 SS V 146 CC PC0/DREQ2 147 PC1/DACK2 148 ...
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PIN DESCRIPTION Circuit Pin no. Pin name type D16 to D23 External data bus bit 16 to bit 23. Enabled in external bus mode P20 to P27 Available as a port in external bus 8-bit mode. ...
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MB91350A Series Circuit Pin no. Pin name type PPG1 PPG timer output pin General purpose I/O. This function is available as a port when the PPG timer out- PN1 put is not in use. PPG2 PPG timer output ...
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Circuit Pin no. Pin name type Data input for serial I/O 7. Since this input is used as required when serial I/O 7 SI7 is in input operation, the port output must remain off unless intentionally turned on. 8/16-bit up/down ...
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MB91350A Series Circuit Pin no. Pin name type External interrupt input. Since this input is used as required when the correspond- INT6 ing external interrupt is enabled, the port output must remain off unless intention- ally turned on. 104 E ...
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Circuit Pin no. Pin name type UART2 data input. Since this input is used as required when UART2 is in input SI2 operation, the port output must remain off unless intentionally turned on. 122 D PH0 General purpose input/output port. ...
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MB91350A Series Circuit Pin no. Pin name type Clock innput/output for serial I/O5. This function is enabled when serial I/O5 is SCK5 using the external shift clock mode, or serial I/O5 clock output function is en- abled. 133 D General ...
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Circuit Pin no. Pin name type Completion output for DMA external transfer. This function is enabled when the DEOP0 external transfer end output for DMA is enabled. Stop input for DMA external transfer. This function is enabled when the external ...
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MB91350A Series Circuit Pin no. Pin name type Chip select 3 output. This function is enabled when the chip select 3 output is en- CS3 abled. 161 C General purpose input/output port. This function is enabled when the chip select ...
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Circuit Pin no. Pin name type Memory clock output. This function is enabled when the memory clock output is MCLK enabled. This outputs the same clock as the external bus operating frequency. (Output halts in sleep/stop mode.) 172 C ...
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MB91350A Series I/O CIRCUIT TYPE Type Standby control X1A X0A B Standby control C Standby control D Standby control 14 Circuit type Clock input Clock input Pull-up control Digital output Digital output Digital input Pull-up control Digital ...
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Type Circuit type E F Standby control G Control H I MB91350A Series • CMOS level output • CMOS level hysteresis input Digital output Digital output With stand voltage Digital input I OL • ...
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MB91350A Series (Continued) Type J 16 Circuit type Control signal Mode input Diffused resistor Remarks • CMOS level input • Flash product only ...
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HANDLING DEVICES • Preventing Latchup Latch-up may occur in a CMOS voltage greater than VCC or less than VSS is applied to an input or output pin above-rating voltage is applied between VCC and ...
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MB91350A Series • Notes on not using the sub clock When no oscillator is connected to the X0A and X1A pins, pull down the X0A pin and open the X1A pin. • Treatment of NC and OPEN pins Pins marked ...
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Sub clock select Immediately after switching from main clock mode to subclock mode for the clock source, insert at least one NOP instruction. (ldi #0x0b, r0) (ldi #_CLKR, r12) stb r0, @r12 // sub-clock mode nop // Must insert ...
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MB91350A Series • Flash memory In programming mode, Flash memory cannot be used as an interrupt vector table. A reset is possible. • Notes on the PS register As the PS register is processed by some instructions in advance, exception ...
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Step execution of RETI command If an interrupt occurs frequently during single-stepping, the corresponding interrupt handling routine is executed repeatedly. This will prevent the main routine and low-interrupt-level programs from being executed. (Whenever RETI is single-stepped ...
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... channels 8/16-bit up/down counter MB91F355A MB91F356B 512 KB (Flash) 256 KB (Flash DREQ0 to DREQ2 DACK0 to DACK2 DEOP0/DSTP0 to DEOP2/DSTP2 IOWR IORD A23 to A00 D31 to D16 RD WR1, WR0 ...
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CPU AND CONTROL UNIT Internal architecture The FR family CPU is a high performance core based on a RISC architecture while incorporating advanced instructions for embedded controller applications. 1. Features • RISC architecture employed. Basic instructions: Executed at 1 instruction ...
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MB91350A Series 2. Internal architecture The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated. The 32-bit/16-bit bus converter is connected to a 32-bit bus (F-bus), providing an interface between the CPU and peripheral ...
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Programming model • Basic programming model GENERAL PURPOSE REGISTERS Program counter program status Table base register Return pointer System stack pointer User stack pointer Multiplication and division result register MB91350A Series 32-bit R0 R1 R12 R13 AC R14 FP ...
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MB91350A Series 4. Register General purpose registers R0 R1 R12 R13 R14 R15 Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory access pointers for CPU operations. Of these 16 registers, the registers ...
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CCR (Condition Code Register ) 7 6 ⎯ ⎯ Stack flag. Cleared to “0” reset Interrupt enable flag. Cleared to “0” reset Negative flag. The initial value after a ...
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MB91350A Series • TBR (Table Base Register) 31 TBR The table base register contains the start address of the vector table used for servicing EIT events. The initial value after a reset is 000FFC00 • RP (Return Pointer ...
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Multiply & Divide registers MDH MDL Multiplication and division result register These registers hold the results of a multiplication or division. Each of them is 32-bit long. The initial value after a reset is indeterminate. MB91350A Series 31 0 ...
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MB91350A Series MODE SETTINGS The FR family uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode. 1. Mode Pins The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed. ...
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WTH1, WTH0 (Bus width setting bits) Used to set the bus width to be used in external bus mode. When the operation mode is the external bus mode, this value is set in bits BW1 and ...
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MB91350A Series MEMORY SPACE 1. Memory space The FR family has logical address space (2 • Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in ...
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Memory Map of MB91354A Single chip mode 0000 0000 H I/O 0000 0400 H I/O 0001 0000 H Access disallowed 0003 E000 H Built-in RAM 8 KB (Executable) 0004 0000 H Built-in RAM 8 KB (Stack) 0004 2000 H ...
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MB91350A Series • Memory Map of MB91356B Single chip mode 0000 0000 H I/O 0000 0400 H I/O 0001 0000 H Access disallowed 0003 E000 H Built-in RAM 8 KB (Executable) 0004 0000 H Built-in RAM 16 KB (Stack) 0004 ...
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I/O Map This shows the location of the various peripheral resource registers in the memory space. (How to read the table) Address + PDR0 [R/W] B PDR1 [R/W] B 000000 H XXXXXXXX XXXXXXXX Read/write attribute, Access ...
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MB91350A Series Address + 0 SMCS6 [R/ 000028 H 00000010 - - - - SMCS7 [R/ 00002C H 00000010 - - - - ⎯ 000030 H CDCR6 [R/W] B 000034 ...
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Address + 0 ADCS2 [R/W] ADCS1 [R/W] 000078 H X000XX00 ADTH0 [ ADTL0 [ 00007C H XXXXXXXX ADTH2 [ ADTL2 [ 000080 H XXXXXXXX ...
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MB91350A Series Address + 0 UTIM [R] H (UTIMR [W] H) 0000CC H 00000000 00000000 EIRR1 [R/ 0000D0 H 00000000 TCDT [R/ 0000D4 H 00000000 00000000 IPCP1 [ 0000D8 H XXXXXXXX XXXXXXXX IPCP3 ...
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Address + 0 PTMR2 [ 000130 H 11111111_11111111 PDUT2 [ 000134 H XXXXXXXX_XXXXXXXX PTMR3 [ 000138 H 11111111_11111111 PDUT3 [ 00013C H XXXXXXXX_XXXXXXXX PTMR4 [ 000140 H 11111111_11111111 PDUT4 [W] ...
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MB91350A Series Address + 0 00022C H to 00023C H 000240 H 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX 000244 H to 00027C H FRLR [R/ 000280 01* 000284 H to 00038C ...
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Address + 0 PCRG [R/W] B PCRH [R/W] B 000420 000000 ⎯ 000424 H PCRO [R/W] B PCRP [R/W] B 000428 H 00000000 00042C H to 00043C H ICR00 [R/ ICR01 [R/ ...
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MB91350A Series Address + 0 WPCR [R/W] B 00048C 000 OSCR [R/W] B 000490 H 000 - - XX0 RSTOP0 [W] B 000494 H 00000000 ⎯ 000498 H 00049C H to 0005FC H ⎯ 000600 ...
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Address + 0 ASR3 [R/ 00064C H 00000000 00000000 ASR4 [R/ 000650 H 00000000 00000000 ASR5 [R/ 000654 H 00000000 00000000 ASR6 [R/ 000658 H 00000000 00000000 ASR7 [R/ 00065C ...
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MB91350A Series Address + 0 EWPT [R] 000B0C H 00000000 00000000 EDTR0 [W] 000B10 H XXXXXXXX XXXXXXXX 000B14 H to 000B1C H 000B20 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B24 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B28 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ...
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Address + 0 000B64 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B68 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B6C H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B70 H to 000BFC H 000C00 H 000C04 H to 000C14 H 000C18 H to 000FFC H 001000 H ...
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MB91350A Series (Continued) Address + 0 FLCR [R/W] 007000 H 0110X000 FLWC [R/W] 007004 H 00010011 ⎯ 007008 H ⎯ 00700C H ⎯ 007010 H 007014 H to 0070FF Test register access barred *2 : The lower ...
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VECTOR TABLE Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception ...
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MB91350A Series Interrupt source DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) A UART4 (Reception completed) SIO 5 SIO 6 SIO 7 UART3 (Reception completed) UART3 (RX completed) Reload timer ...
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Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction MB91350A Series Interrupt Interrupt number ...
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MB91350A Series PERIPHERAL RESOURCES 1. Interrupt controller (1)Description The interrupt controller manages interrupt reception and arbitration. • Hardware configuration This module consists of the following components: • ICR register • Interrupt priority determination circuit • Interrupt level and interrupt number ...
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ICR16 ⎯ ICR17 ⎯ ICR18 ⎯ ICR19 ⎯ ICR20 ⎯ ICR21 ⎯ ICR22 ⎯ ICR23 ⎯ ICR24 ⎯ ICR25 ⎯ ICR26 ⎯ ICR27 ⎯ ICR28 ⎯ ICR29 ⎯ ICR30 ⎯ ICR31 ⎯ ICR32 ⎯ ICR33 ⎯ ICR34 ...
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MB91350A Series (3)Block diagram UNMI NMI RI00 52 ("1" when LEVEL WAKEUP Determine order of priority 5 NMI LEVEL determination LEVEL, VECTOR ICR00 Genera- tion VECTOR 6 determination R-bus ≠ 11111) LEVEL4 to LEVEL0 HLDREQ MHALTI Cancel NMI request VCT5 ...
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External interrupt/NMI control (1)Description The external interrupt control unit is the block that controls external interrupt requests input to NMI and INT0 to INT15. The level can be selected from “H”, “L”, rising edge, or falling edge (except for ...
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MB91350A Series 3. REALOS-related Hardware REALOS-related hardware is used by the real-time OS. Therefore, REALOS-related hardware cannot be used by user programs when REALOS is used. • Delay interrupt module (1)Description The delayed interrupt module generates a task switching interrupt. ...
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Bit Search Module (1)Description The bit search module searches data written to an input register for “0”, “1” change point and returns the detected bit position. (2)Register list 0 detection data register (BSD0) 1 detection data register ...
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... This block is the up/down counter consisting of 6 event input pins, an 8/16-bit up/down counter, an 8-bit reload/ compare register, and their control circuit. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 2 channels of 8/16-bit up/down counter in this block. This module has the following features. • 8-bit count register enabling counting from (0)d to (255)d (enabling counting from (0)d to (65535)d in "16-bit x 1 operation mode" ...
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Up/down count resister (UDCR) Up/down count resister ch0 (UDCR0) 7 D07 Up/down count resister ch1 (UDCR1) 15 D15 • Reload compare resister (RCR) Reload compare resister ch0 (RCR0) 7 D07 Reload compare resister ch1 (RCR1) 15 D15 ...
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MB91350A Series (3)Block diagram CGE CGE Edge/level detection ZIN0, ZIN1 CES CM Up/down count AIN0, AIN1 clock BIN0, BIN1 select Prescaler CLK 58 Data bus 8 bit RCR0(Reload CGS compare register ch0 Reload CTU control UC RLD Counter clear UD ...
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... The clock source can be selected from among three internal clocks (prepared by frequency dividing the machine clock by 2/8/32, and also by 64/128 only for ch3) and an external event. The interrupt can be used to initiate DMA transfer. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 4 channels of this timer. (2)Register list Control status register (TMCSR) 15 ⎯ ...
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MB91350A Series (3)Block diagram 16-bit reload register (TMRLR 16-bit timer register (TMR) UF Count enable Clock selector φ φ φ φ φ ...
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... PPG (Programable Pulse Generator) The PPG can efficiently output highly precise PWM waveforms. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 6 channels of PPG timer. (1)Description Each channel consists of a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare register with duty ratio setting buffer, and pin control unit. ...
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... Description The U-Timer is a 16-bit timer for generating the baud rate for the UART. An arbitrary baud rate can be set depending on the combination of the chip operating frequency and U-Timer reload value. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5 channels of this timer. (2) Register list U-Timer Register (UTIM) ...
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... UART (1) Description The UART is a serial I/O port for asynchronous (start-stop) or CLK synchronous communication. This module has the features listed below. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5 channels of UART. • Full duplex double buffer • Asynchronous (start-stop synchronized) or CLK synchronized transmission • Supports multi-processor mode • ...
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MB91350A Series (3) Block diagram Control signal From U-Timer Clock selection circuit External clock SCK SI (Receive data) Receive status decision circuit For DMA received error generating signal (to DMAC) MD1 MD0 SMR Register CS0 64 Transmission clock Reception clock ...
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... This block is a serial I/O interface that allows data transfer using clock synchronization composition of a single 8-bit × 1 channel. LSB-first or MSB-first transfer mode can be selected for data transfer. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 3 channels of this SIO. The serial I/O interface operates in 2 modes: • Internal shift clock mode: Transfer data in synchronization with the internal clock. ...
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MB91350A Series (3)Block diagram (MSB fast SI5 to SI7 SDR (Serial Data Register) SO5 to SO7 SCK5 to SCK7 Internal clock 2 SMD2 SMD1 SMD0 66 Internal data bus (MSB fast Select transmitting direction ...
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The 16-bit free-running timer consists of a 16-bit up counter, control register, and status register. The count values of this timer are used as the base timer for the output compares and input capture modules. ...
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MB91350A Series 11. Input Capture (1) Description This module detects a rising or falling edge or both edges of an external input signal and stores the 16-bit free- running timer value in a register. This module stores the 16-bit free-running ...
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Block diagram 16-bit timer counter value (T15 to T00) Input capture data register ch (0, 2) 16-bit timer counter value (T15 to T00) Input capture data register ch (1, 3) MB91350A Series Edge detection EG11 EG10 EG01 EG00 EG31 ...
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... When the 16-bit free-running timer value matches the compare register value, the output level is inverted and an interrupt is issued. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 8 channels of this block. This module has the features listed below. • Capable of using the 8 compare registers independently. Output pins and interrupt flags corresponding to the compare registers • ...
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Block diagram (Only ch0 is used as a free running timer clear register.) Output compare register Compare circuit Output compare register Compare circuit CST1 CST0 16-bit free-run timer MB91350A Series OTD1 OTD0 Compare OTE0, OTE2, OTE4, OTE6 Output latch ...
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MB91350A Series 13 Interface (1) Description The interface is a serial I/O port supporting the Inter-IC bus, operating as a master/slave device on the I bus. It has the following features • Master/slave sending ...
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Bus control register(IBCR BER BEIE Bus status register(IBSR RSC 10-bit slave address resister (ITBA ⎯ ⎯ TA7 TA6 10-bit slave address mask resister(ITMK ENTB RAL 7 6 ...
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MB91350A Series (3) Block diagram ICCR EN IDBL DBL ICCR CS4 CS3 CS2 CS1 CS0 IBSR BB RSC LRB TRX ADT AL IBCR BER BEIE INTE INT IBCR SCC MSS ACK GCAA IBSR AAS GCA ISMK FNSB ITMK ENTB 74 ...
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A/D Converter (1) Description The A/D converter converts the analog input voltage into a digital value. It has the following features: • Conversion time: 1.48 µs minimum per channel • Employing serial/parallel conversion type for sample & hold circuit ...
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MB91350A Series (3) Block diagram Analog input AN0 AN1 AN2 AN3 AN4 M AN5 P AN6 X AN7 AN8 AN9 AN10 AN11 16-bit reload timer ch2 External input AVRH, AV /AVRL bit P ...
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D/A Converter (1) Description This block contains 2 channels of 8-bit D/A converters. The D/A converter register can be used to control the independent output of each channel. The block has the following features. • Power saving function ...
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MB91350A Series 16. DMAC (DMA Controller) (1) Description This module realize direct memory access (DMA) transfer with the FR family device. DMA transfer controlled by this module enables many types of data transfer to be performed at high speed without ...
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Register Description Ch0 control/status Ch1 control/status Ch2 control/status Ch3 control/status Ch4 control/status Overall control register Ch0 transfer source address register Ch1 transfer source address register Ch2 transfer source address register Ch3 transfer source address register Ch4 transfer source address ...
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MB91350A Series (3) Block diagram DMA transfer request to bus controller Read/write Read Write control DDNO T o bus con- troller Access Address 80 Counter DMA start Buffer source select circuit & request acceptance Selector control DTC two-stage register DTCR ...
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ELECTRICAL CHARACTERISTICS 1. Abusolute Maximum Rating Parameter Power supply voltage* 1 Analog power supply voltage Analog power supply voltage* Analog reference voltage* 1 Input voltage Input voltage (Nch open-drain) * Analog pin input voltage* 1 Output ...
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MB91350A Series *7 : • Relevant pins: Port2 and AN (A/D input) • Use within recommended operating conditions. • Use at ...
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... No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Value Min Max 3 ...
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MB91350A Series 3. DC Characteristics Sym- Parameter Pin bol Port Port “H” level V MD0, MD1, IHS input voltage MD2, INIT, ...
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Sym- Parameter Pin bol CCS I CCH Power supply V CC current I CCL I CCLS I CCT Other than Input capacitance ...
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MB91350A Series 4. AC Characteristics (1) Clock timing Sym- Parameter Pin bol Clock frequency X1 X0 Clock cycle time Clock frequency Internal operating ⎯ f CPP clock frequency ...
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Conditions for measuring the clock timing ratings • Operation Assurance Range V (V) CC 3.6 3.0 0 2.94 Internal clock MB91350A Series 0 Output pin 0 ...
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MB91350A Series • External/internal clock setting range (MHz CPP 25 f CPT 12 Notes : • When the PLL is used, the external clock input must fall between 10.0 and 12.5 MHz. ...
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Parameter Symbol Cycle time t CYC SYSCLK ↑→ SYSCLK ↓ t CHCL SYSCLK ↓→ SYSCLK ↑ t CLCH * the frequency of one clock cycle after gearing. CYC *2 : The following ratings are ...
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MB91350A Series (4) Normal bus access read/write operation Parameter Symbol t CSLCH CS0 to CS3 setup t CSDLCH CS0 to CS3 hold t CHCSH t ASCH Address setup t ASWL t ASRL t CHAX Address hold t WHAX t RHAX ...
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CYC BA1 V OH MCLK (LBA) CS0 to CS3 A23 to A00 RD D31 to D16 WR0, WR1 D31 to D16 MB91350A Series ASLCH t CHASH CSLCH V ...
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MB91350A Series (5) Multiplex bus access read/write operation Parameter Symbol AD15 to AD0 Address AUDI setup time t → MCLK ↑ MCLK ↑ → AD15 to AD0 Address t AUDI Hold Time AD15 to AD0 Address t AUDI setup time ...
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Ready input timings Parameter Symbol RDY setup time → t RDYS MCLK ↓ MCLK ↑ → t RDYH RDY hold time MCLK RDY with wait RDY without wait MB91350A Series = 3 3 ...
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MB91350A Series (7) Hold timing Parameter Symbol BRQ setup time t BRQS → MCLK ↑ MCLK ↑ → BRQ t BRQH AUDI Hold Time BGRNT delay time t CHBGL BGRNT delay time t CHBGH Pin floating → t XZBGL BGRNT ...
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UART, SIO timing Parameter Symbol Serial clock cycle time t SCYC SCK ↓ → t SLOV BGRNT delay time Valid SI → SCK ↑ t IVSH SCK ↑ → valid SIN hold t SHIX time Serial clock H Pulse ...
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MB91350A Series (9) Free-run timer clock, PPG timer input timing Parameter Symbol t TIWH Input pulse width t TIWL Note : t indicates the peripheral clock cycle time. See “(1) Clock timing”. CPP (10) Trigger input timing Parameter Symbol A/D ...
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For edge detection (block/step transfer mode,burst transfer mode) Parameter Symbol DREQ Input pulse width t DRWL DREQ Input pulse width t DSWH * : t becomes t when f is greater than f CYC CP CPT ...
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MB91350A Series V OH MCLK V OL DREQ0 to DREQ2 DSTP0 to DSTP2 IORD IOWR RD, WRn Chip select timing t DALCH t DADLCH DACK0 to DACK2 V t DELCH t DEDLCH DEOP0 to DEOP2 V FR30 compatible timing DACK0 ...
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Timing Parameter SCL clock frequency* 4 Hold time (repeated) START condition SDA↓→SCL↓ “L” width of the SCL clock “H” width of the SCL clock Set-up time for a repeated START condition SCL↑→SDA↓ Data hold time SCL↓→SDA↓↑ ...
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MB91350A Series 5. Electrical Characteristics for the A/D Converter = Parameter Resolution 1 Total error* Nonlinear error* 1 Differential linear error* 1 Zero transition voltage* 1 Full-transition voltage* 1 ...
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... During Sampling : ON MB91355A MB91F355A MB91F356B (External impedance = 0 kΩ kΩ MB91355A MB91350A Series R C 0.18 kΩ (Max) 63.0 pF (Max) 0.18 kΩ (Max) 39.0 pF (Max) 0.18 kΩ (Max) 39.0 pF (Max) MB91F355A/MB91F356B MB91355A Minimum sampling time [µs] 101 ...
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MB91350A Series Definition of A/D Converter Terms • Resolution Analog variation that is recognized by an A/D converter. • Linearity error Zero transition point ( "0000000000” - “0000000001”) and full-scale transition point Difference between the line connected (“1111111110” - “1111111111”) ...
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Total error This error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error. 3FF H 3FE H 3FD H 004 H 003 H 002 H 001 H AV AVRH − AV 1LS’ ...
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MB91350A Series 6. Electrical Characteristics for the D/A Converter Parameter Symbol ⎯ Resolution ⎯ Nonlinear error ⎯ Differential linear error ⎯ Convertion speed ⎯ ⎯ Output high impedance ⎯ Analog current I ADA I ADAH * : This D/A converter ...
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FLASH MEMORY WRITE/ERASE CHARACTERISTICS Parameter Condition Sector erase time Ta = +25 °C, Chip erase time = 3 Half word (16-bit width) writing time ⎯ Write/erase cycle Flash data retention Average Ta = +85°C time *: This ...
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MB91350A Series EXAMPLE CHARACTERISTICS (1) “H” level output voltage 2.7 3.0 3.3 V [V] CC (3) “L” level output voltage (Nch open-drain OL2 CC 500 400 300 ...
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Power supply current +25 ° CCP CPT 300 250 200 150 100 50 0 2.7 3.0 3.3 V [V] CC (8) Power supply current at sleep I - ...
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MB91350A Series (Continued) (14) A/D converter power supply current 2.7 3.0 3.3 V [V] CC (16) A/D converter power supply current at stop ...
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... ORDERING INFORMATION Part number MB91F355APMT-002 MB91F356BPMT MB91355APMT MB91354APMT MB91350A Series Package 176-pin plastic LQFP (FPT-176P-M02) 176-pin plastic LQFP (FPT-176P-M02) 176-pin plastic LQFP (FPT-176P-M02) 176-pin plastic LQFP (FPT-176P-M02) Remarks Lead-free Package Lead-free Package Lead-free Package Lead-free Package 109 ...
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... INDEX 176 LEAD No. 1 0.50(.020) 2003 FUJITSU LIMITED F176006S-c-4-6 C 110 Note Values do not include resin protrusion. Resin protrusion is +0.25 (.010) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. ...
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... Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. ...