K8P3215UQB Samsung, K8P3215UQB Datasheet
K8P3215UQB
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K8P3215UQB Summary of contents
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... K8P3215UQB 32Mb B-die Page NOR Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... Program Time is changed from 4ns to 6ns. -Accelerated Quad Word Program Time is changed from 1.2ns to 1.5ns. 0.2 - Die version is changed E-die to B-die (K8P3215UQE --> K8P3215UQB) 0.3 -64FBGA 13x11 with 1.0mm Ball Pitch is added. -56FBGA is deleted. -48FBGA 6x8.5 is deleted. -56TSOP 20x14 is deleted. -CFI code is changed ...
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... The K8P3215UQB NOR Flash consists of four banks. This device is capable of reading data from one bank while programming or erasing in the other banks. The K8P3215UQB offers fast page access time of 20~30ns with random access time of 55~70ns. The device′s fast access , ...
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... K8P3215UQB PIN CONFIGURATION A15 1 A14 2 A13 3 A12 4 A11 5 A10 A19 9 48-pin TSOP1 A20 Standard Type RESET 12 N.C 13 12mm x 20mm WP/ACC 14 RY/BY 15 A18 16 A17 FLASH MEMORY 48 A16 47 N.C Vss 46 45 DQ15 44 DQ7 43 DQ14 ...
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... K8P3215UQB 64 Ball FBGA TOP VIEW (BALL DOWN A13 A12 RESET RY/BY WP/ACC A7 A17 Vss NC NC A14 A15 A16 NC DQ15 A10 A11 DQ7 DQ14 DQ13 NC DQ12 Vcc A19 DQ5 A18 DQ10 DQ11 A20 DQ2 A6 A5 DQ0 DQ8 DQ9 ...
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... K8P3215UQB Vss 48 Ball FBGA TOP VIEW (BALL DOWN) FUNCTIONAL BLOCK DIAGRAM Bank 0 Address Vcc Vss CE OE Bank 1 I/O Address Interface WE & Bank RESET Control Bank 3 RY/BY Address WP/ACC A0~A20 DQ0~DQ15 RY A13 ...
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... Vcc VIO (1) Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) Max. Page Access Time (ns) Notes : 1. Only speed options can be provided in case of using 1.65~1.95V V K8P3215UQB DEVICE BANK DIVISIONS Table 2. Bank 0, Bank 3 Mbit Block Sizes and 4 Mbit Table 3 ...
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... K8P3215UQB K8P3215UQB DEVICE BANK DIVISIONS Table 4. Bank Number of Blocks FLASH MEMORY Block Size 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords Revision 1.1 April 2007 ...
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... The command set of K8P3215UQB is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), out- put enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing ...
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... K8P3215UQB COMMAND DEFINITIONS The K8P3215UQB operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg- ister. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode ...
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... The data is DQ6=1 for customer locked and DQ7=1 for factory locked. 11. Reset command returns device to reading array. 12. Cycle 4 programs the addressed locking bit. Cycle 5 and 6 validate bit has been fully programmed when DQ0=1. If DQ0=0 in cycle 6, program command must be issued and verified again. K8P3215UQB Autoselect Codes Table 7. A20 Description ...
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... DEVICE OPERATION Read Mode The K8P3215UQB is controlled by Chip Enable (CE), Output Enable (OE) and Write Enable (WE). When CE and OE are low and WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state whenever high. The K8P3215UQB is available for Page mode. Page mode provides fast access time for high perfor- mance system ...
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... Program The K8P3215UQB can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written ...
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... However, a succeeding read will show that the data is still ’0’. Only erase operations can convert a ’0’ ’1’. Unlock Bypass The K8P3215UQB provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and chip erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command sequence ...
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... K8P3215UQB WE 555H 2AAH Address DQ15-DQ0 AAH RY/BY Figure 6. Block Erase Command Sequence Erase Suspend / Resume The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Sus- pend command is only valid during the Block Erase operation including the time window of 50us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running ...
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... Read While Write The K8P3215UQB provides multi-bank memory architecture that divides the memory array into four banks. The device is capable of reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with multi-bank architecture ...
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... K8P3215UQB Power-up Protection To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the read mode. Low Vcc Write Inhibit To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 2.3V. If Vcc < ...
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... K8P3215UQB High Voltage Block Protection Block protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (Vid placed on the RESET# pin. Refer to Figure 8 for details on this procedure. Note that for block unprotect, all unprotected blocks must first be protected prior to the first sector write cycle. ...
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... K8P3215UQB Block Protect Algorithm Set up Block Group address Block Group Protect: Write 60H to Block Group address with A6=0,A1=1 A0=0 Wait 120µs Verify Block Group Protect:Write 40H to Block Group address with A6=0, Increment A1=1,A0=0 COUNT Read from Block Group address with A6=0, A1=1,A0 COUNT Data=01h? =25? ...
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... Block Protection The K8P3215UQB features several levels of block protection, which can disable both the program and erase operations in certain blocks or block groups: Persistent Block Protection A command block protection method that replaces the old 12 V controlled protection method. Password Block Protection ...
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... K8P3215UQB The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the block PPBs prior to PPB erasure. Otherwise, a previously erased block PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing block PPBs over-erasure. ...
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... K8P3215UQB If the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. A program command to a protected block enables status polling for approximately 1us before the device returns to read mode without having modified the contents of the protected block. An erase command to a protected block enables status polling for approximately 50us after which the device returns to read mode without having erased the protected block ...
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... K8P3215UQB If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword blocks on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two blocks to whether they were last set to be protected or unprotected. That is, block protection or unprotection for these sectors depends on whether they were last pro- tected or unprotected using the method described in the " ...
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... K8P3215UQB K8P3215UQB Table 9. Boot Block/Block Addresses for Protection / Unprotection Block BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11-BA14 BA15-BA18 BA19-BA22 BA23-BA26 BA27-BA30 BA31-BA34 BA35-BA38 BA39-BA42 BA43-BA46 BA47-BA50 BA51-BA54 BA55-BA58 BA59-BA62 BA63-BA66 BA67 BA68 BA69 BA70 BA71 BA72 ...
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... K8P3215UQB Table 10. Block Protection Command Sequences Cycl Command Sequence 1st Cycle Add 555H Password Program(1,2) 4 Dat AAH Add 555H Password Verify(2,4,5) 4 Dat AAH Add 555H r Password Unlock(3,6,7) 7 Dat AAH Add 555H r PPB Program(1,2,8) 6 Dat AAH Add 555H r Master locking bit Set ...
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... K8P3215UQB X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit Notes: • See the description of bus operations. • All values are in hexadecimal. • Shaded cells in table denote read cycles. All other cycles are write operations. ...
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... K8P3215UQB Table 11. Common Flash Memory Interface Code Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max ...
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... K8P3215UQB Table 11. Common Flash Memory Interface Code Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1- Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported Read Only Read & Write Block Protect ...
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... K8P3215UQB DEVICE STATUS FLAGS The K8P3215UQB has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. The statuses are as follows : Table 12 ...
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... When the RY/ BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the K8P3215UQB is placed in an Erase Suspend mode, the RY/ BY output will be High. For programming, the RY valid (RY after the rising edge of the fourth WE pulse in the four write pulse sequence ...
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... K8P3215UQB Start Read(DQ0~DQ7) Valid Address DQ7 = Data ? Yes No No DQ5 = 1 ? Yes Read(DQ0~DQ7) Valid Address Yes DQ7 = Data ? No Fail Figure 9. Data Polling Algorithms Read(DQ0~DQ7) Read(DQ0~DQ7) No Read twice(DQ0~DQ7) Pass 31 FLASH MEMORY Start Valid Address Valid Address DQ6 = Toggle ? No Yes DQ5 = 1 ? Yes Valid Address ...
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... K8P3215UQB ABSOLUTE MAXIMUM RATINGS Parameter Vcc A9, RESET Voltage on any pin relative WP/ACC All Other Pins Commercial Temperature Under Bias Extended Storage Temperature Short Circuit Output Current Operating Temperature Notes : 1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on input / output pins is Vcc+0.5V which, during transitions, may overshoot to Vcc+2.0V for periods < ...
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... K8P3215UQB Parameter Symbol Voltage for Autoselect and V ID Block Protect (4) Output Low Level V OL Output High Level V OH Low VCC Lock-out Voltage (5) V LKO Notes : 1. The I current listed includes both the DC operating current and the frequency dependent component(at 10 MHz active during Internal Routine(program or erase progress. ...
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... K8P3215UQB AC CHARACTERISTICS Write(Erase/Program)Operations Alternate WE Controlled Write Parameter Symbol Write Cycle Time ( Address Setup Time t ASO t AH Address Hold Time t AHT Data Setup Time t DS Data Hold Time t DH Output Enable Setup Time (1) t OES Output Read (1) t OEH1 Enable ...
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... K8P3215UQB AC CHARACTERISTICS Write(Erase/Program)Operations Alternate CE Controlled Writes Parameter Symbol Write Cycle Time ( Address Setup Time t AS Address Hold Time t AH Data Setup Time t DS Data Hold Time t DH Output Enable Setup Time t OES (1) Out- Read (1) t OEH1 put Toggle and Data ...
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... K8P3215UQB SWITCHING WAVEFORMS Conventional Read Operations Address HIGH-Z Outputs HIGH RY/BY Parameter Symbol Read Cycle Time t RC Address Access Time t AA Chip Enable Access Time t CE Output Enable Time & OE Disable Time ( Output Hold Time from t OH Address ...
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... K8P3215UQB SWITCHING WAVEFORMS Page Read Operations A3 to A20 OEH OE WE High-Z Output Figure 12. Page Read Operation Timings Parameter Symbol Read Cycle Time t RC Page Read Cycle Time t PRC Address Access Time t AA Page Address Access Time t PA Chip Enable Access Time ...
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... K8P3215UQB SWITCHING WAVEFORMS Hardware Reset/Read Operations Address RESET High-Z Outputs Figure 13. Hardware Reset/Read Operation Timings Parameter Symbol Read Cycle Time t RC Address Access Time t AA Chip Enable Access Time t CE Output Hold Time from t OH Address RESET Pulse Width ...
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... K8P3215UQB SWITCHING WAVEFORMS Alternate WE Controlled Program Operations Alternate WE Controlled Program Operations 555H Address CE t OES WPH A0H DATA t DS RY/BY Notes : 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. ...
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... K8P3215UQB SWITCHING WAVEFORMS Alternate CE Controlled Program Operations 555H Address WE t OES A0H DATA t DS RY/BY Figure 15. Alternate CE Controlled Program Operation Timings Notes : 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. ...
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... K8P3215UQB SWITCHING WAVEFORMS Chip/Block Erase Operations t AS 555H 2AAH Address CE t OES WPH AAH DATA t DS RY/BY Vcc t VCS Figure 16. Chip/Block Erase Operation Timings Parameter Symbol Write Cycle Time t WC Address Setup Time t AS Address Hold Time ...
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... K8P3215UQB SWITCHING WAVEFORMS Read While Write Operations Read Command DA2 Address DA1 (555H OES Valid Valid DQ Output Input (A0H) Figure 17. Read While Write Operation Timings Note : This is an example in the program-case of the Read While Write function. ...
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... K8P3215UQB SWITCHING WAVEFORMS Data Polling During Internal Routine Operation OEH WE Data In DQ7 DQ0-DQ6 Data In Note : *DQ7=Vaild Data (The device has completed the internal operation). Figure 18. Data Polling During Internal Routine Operation Timings RY/BY Timing Diagram During Program/Erase Operation CE WE RY/BY Figure 19. RY/BY Timing Diagram During Program/Erase Operation Timings ...
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... K8P3215UQB SWITCHING WAVEFORMS Toggle Bit During Internal Routine Operation Address OEH Data In DQ6/DQ2 RY/BY Note : Address for the write operation must include a bank address (A19~A20) where the data is written. Enter Embedded Erase Erasing Suspend Erase Toggle DQ and DQ ...
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... K8P3215UQB SWITCHING WAVEFORMS RESET Timing Diagram High RY/ RESET RY/ RESET Power-up and RESET Timing Diagram RESET Vcc Address DATA Figure 21. Power-up and RESET Timing Diagram Sym- Parameter bol RESET Pulse Width t RP RESET Low to Valid Data t READY (During Internal Routine) ...
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... K8P3215UQB SWITCHING WAVEFORMS Block Group Protect & Unprotect Operations RESET BGA,A6 A1,A0 Block Group Protect / Unprotect DATA 60H 1µ RY/BY Notes : Block Group Protect (A6= Block Group Unprotect (A6= BGA = Block Group Address (A12 ~ A20) Temporary Block Group Unprotect RESET ...
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... K8P3215UQB SWITCHING WAVEFORMS Unlock Bypass Program Operations(Accelerated Program Address DQ0-DQ15 OE 1us VPP Unlock Bypass Block Erase Operations CE WE Address DQ0-DQ15 OE 1us VPP Notes can be left high for subsequent programming pulses. ...
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... K8P3215UQB SWITCHING WAVEFORMS Quad word Accelerated Program CE WE Address Don’t Care DQ15-DQ0 Don’t Care OE 1us VPP Notes can be left high for subsequent programming pulses Use setup and hold times from conventional program operations. ...
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... K8P3215UQB Table 13. Block Architecture ( K8P3215UQB Bank Block BA77 BA76 BA75 BA74 BA73 BA72 BA71 Bank 3 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 Bank 2 BA50 BA49 BA48 BA47 BA46 ...
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... K8P3215UQB Table 13. Block Architecture ( K8P3215UQB Bank Block BA38 BA37 BA36 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 Bank 1 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 Bank0 ...
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... K8P3215UQB PACKAGE DIMENSIONS 64-Ball Fine Ball Grid Array Package (measured in millimeters) Top View 11.00 ±0.10 #A1 0.10 MAX Bottom View 11.00 ±0.10 1.00 x 7=7.00 1.00 (Datum (Datum B) 0.50 64- ∅ 0.60Solder Ball (POST REFLOW ∅ 0.62 ) ±0.05 ∅ 3.50 0 Side View 13.00 51 FLASH MEMORY A #A1 INDEX MARK ...
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... K8P3215UQB PACKAGE DIMENSIONS 48-Ball Fine Ball Grid Array Package (measured in millimeters) Top View 6.00 ±0.10 #A1 0.10MAX NOTE 48FBGA 6x8 Package has same ball configuration with 48FBGA 6x9 Package of Dual Die Package. FLASH MEMORY Bottom View 6.00 ±0.10 0.80 x 5=4. (Datum A) 0.80 A (Datum B) ...
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... K8P3215UQB PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8’C 0.45~0.75 0.018~0.030 20.00 ±0.20 0.787 ±0.008 #48 #25 18.40 ±0.10 0.724 ±0.004 0.50 ( 0.020 53 FLASH MEMORY Unit :mm/Inch 1.00 0.05 ±0.05 MIN 0.039 0.002 ±0.002 1.20 MAX 0.047 ) Revision 1.1 April 2007 ...