K7Q161852A-FC16 Samsung, K7Q161852A-FC16 Datasheet
K7Q161852A-FC16
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K7Q161852A-FC16 Summary of contents
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... K7Q163652A K7Q161852A Document Title 512Kx36-bit, 1Mx18-bit QDR Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Amendment 1) Page 3,4 PIN NAME DESCRIPTION W (4A) : from Read Control Pin to Write Control R (8A) : from Write Control Pin to Read Control BW (7B) BW (7A from Read Control Pin to Byte Wrtie Control ...
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... QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology. 512Kx36 & 1Mx18 QDR SRAM TM Organization Number K7Q163652A-FC16 X36 K7Q163652A-FC13 K7Q163652A-FC10 K7Q161852A-FC16 X18 K7Q161852A-FC13 K7Q161852A-FC10 36 (or 18) 36 (or 18) WRITE DRIVER 512Kx36 72 1Mx18 ...
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... K7Q163652A K7Q161852A PIN CONFIGURATIONS (TOP VIEW) K7Q161852A(1Mx18 /SA* NC/SA D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 ...
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... K7Q163652A K7Q161852A PIN CONFIGURATIONS (TOP VIEW /SA* NC/SA Q27 Q18 D18 C D27 Q28 D19 D D28 D20 Q19 E Q29 D29 Q20 F Q30 Q21 D21 G D30 D22 Q22 REF DDQ J D31 Q31 D23 K Q32 D32 Q23 L Q33 Q24 D24 ...
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... And pipelined data are transferred out of device on every rising edge of both C and C clocks. In case C and C tied to high, output data are triggered by K and K instead of C and C. When the R is disabled after a read operation, the K7Q163652A and K7Q161852A will first complete burst read operation before entering into deselect mode at the next K clock rising edge. ...
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... SRAM needs 1024 non-read cycles. Single Clock Mode The K7Q163652A and K7Q161852A can be used with the single clock pair K and K. In this mode, C and C must be tied high during power up and this single clock pair control both the input and output registers. ...
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... K7Q163652A K7Q161852A READ NOP READ LOAD NEW READ READ ADDRESS ALWAYS (FIXED) DDR READ Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1. 2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case. ...
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... K7Q163652A K7Q161852A TRUTH TABLES SYNCHRONOUS TRUTH TABLE D(A0) Stopped X X Previous state Din at K(t) Notes means "Don t Care". 2. The rising edge of clock is symbolized Before enter into clock stop status, all pending read and write operations will be completed. ...
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... K7Q163652A K7Q161852A ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on V Supply Relative to V DDQ SS Voltage on Input Pin Relative Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... K7Q163652A K7Q161852A Overershoot Timing 20% t (MIN) KHKH V +0.7V DDQ V DDQ V IL Note: For power-up +0.3V and V 2.4V and V IH DDQ DD OPERATING CONDITIONS (0 C PARAMETER Supply Voltage Reference Voltage Ground AC TIMING CHARACTERISTICS PARAMETER Clock Clock Cycle Time( Clock HIGH time ( Clock Low time ( ...
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... K7Q163652A K7Q161852A AC TEST CONDITIONS Parameter Symbol Core Power Supply Voltage V DD Output Power Supply Voltage V DDQ Input High/Low Level Input Reference Level V REF Input Rise/Fall Time Output Timing Reference Level Note: Parameters are tested with RQ=250 PIN CAPACITANCE PRMETER ...
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... K7Q163652A K7Q161852A TIMING WAVE FORMS OF READ AND NOP READ READ t KHKH t KLKH K t KHKL IVKH KHIX R Q(Data Out) t KHCH C C Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0. 2. Outputs are disabled(High-Z) one cycle after a NOP. ...
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... K7Q163652A K7Q161852A TIMING WAVE FORMS OF READ, WRITE AND NOP READ WRITE READ D(Data In) D2-1 D2-2 D4-1 Q(Data Out Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0. 2. Outputs are disabled(High-Z) one cycle after a NOP. ...
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... K7Q163652A K7Q161852A IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control ...
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... K7Q163652A K7Q161852A SCAN REGISTER DEFINITION Part Instruction Register 1Mx18 3 bits 512Kx36 3 bits ID REGISTER DEFINITION Revision Number Part (31:28) 1Mx18 0000 512Kx36 0000 BOUNDARY SCAN EXIT ORDER BIT PIN 11P 11 10P 12 10N 13 9P ...
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... K7Q163652A K7Q161852A JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL Note: 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7Q163652A K7Q161852A 165 FBGA PACKAGE DIMENSIONS 13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array Symbol Value Units 1.3 0 0.35 0.05 mm 512Kx36 & 1Mx18 QDR Note Symbol Value E 1.0 F 14.0 G 10 SRAM Top View ...