ZL50409GDC Zarlink Semiconductor, ZL50409GDC Datasheet
ZL50409GDC
Related parts for ZL50409GDC
ZL50409GDC Summary of contents
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... EEPROM Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. Managed 9-Port 10/100M Ethernet Switch Ordering Information ZL50409GDC • Supports both shared VLAN learning (SVL) and independent VLAN learning (IVL) • ...
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... Backpressure flow control for Half Duplex ports • Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports • Built-in reset logic triggered by system malfunction • Built-In Self Test for internal SRAM • IEEE-1149.1 (JTAG) test port ZL50409 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network management solution. The ZL50409 is fabricated using 0.18 micron technology. The ZL50409 is packaged in a 208-pin Ball Grid Array package. ZL50409 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.1 MAC Search 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 MAC Address Filtering 5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ZL50409 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... MMAC Reference Clock (REF_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.4 JTAG Test Clock (TCK) speed requirements 10.2 Clock Generation 10.2.1 MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.3 Ethernet Interface Clocks 11.0 Hardware Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2 IEEE 802.3 HUB Management (RFC 1516 11.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.1.3 FCSErrors 11.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ZL50409 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... BUF_LIMIT – Frame Buffer Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.3.1.6 FCC – Flow Control Grant Period 12.3.2 (Group 1 Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.1 AVTCL – VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.2 AVTCH – VLAN Type Code Register High 12.3.2.3 PVMAP00_0 – Port 0 Configuration Register ZL50409 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...
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... RDRC1 – WRED Rate Control 12.3.6.7 RDRC2 – WRED Rate Control 12.3.6.8 SFCB – Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.9 C1RS – Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.10 C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.11 C3RS – Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.6.12 AVPML – VLAN Tag Priority Map ZL50409 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.1 MIRROR CONTROL – Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.2 MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0 100 12.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0 100 12.3.8.4 RMAC_MIRROR0 – RMAC Mirror 100 ZL50409 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...
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... DA – Dead or Alive Register 114 13.0 Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1 Absolute Maximum Ratings 115 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.4 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.2 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 ZL50409 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...
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... I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.4.7 Serial Interface Setup Timing 123 13.4.8 JTAG (IEEE 1149.1-2001 124 14.0 Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.1 July 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.2 November 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3 February 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.4 August 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.5 November 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ZL50409 Table of Contents 10 Zarlink Semiconductor Inc. Data Sheet ...
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... M3_TX M3_TX M4_RX M4_C M4_TX GND Zarlink Semiconductor Inc. Data Sheet P_DAT P_DAT REF_C RSVD M9_M M9_TX A13 A15 LK TXCLK EN P_DAT P_DAT TCK TMS RSVD M9_RX A12 A14 CK TSTO ...
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... Input CPU Bus-Write Enable with pull-up Input CPU Bus-Read Enable Input Chip Select with pull-up Output CPU Interrupt Ports [7:0] – Receive Data Bit [3:0] with pull-up Ports [7:0] – Carrier Sense and Receive Data with pull-up Valid 12 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Input Collision Detected with pull-down Input or Output Receive Clock with pull-up This pin in an output if ECR4P9[1]='1' Input Receive Data Bit [3:0] with pull-up Output Transmit Data Enable with pull-up Input Transmit Clock with pull-up 13 Zarlink Semiconductor Inc. Data Sheet Description ...
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... SCLK needs to operate at difference frequency. SCLK requires 40/60% duty cycle clock. Power +1.8 Volt DC Supply Power +3.3 Volt DC Supply Power Ground Ground Input Reset Input Output Reset PHY Output MII Management Data Clock I/O-TS MII Management Data I/O with pull-up 14 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Pulldown: Installed Input (Reset Only) Manufacturing Option. Must be pulled up. Must be externally pulled-up Input (Reset Only) Module Detect Pullup: Enable. In this mode, the device will detect the existence of a PHY (for hot swap purpose). Pulldown: Disable 15 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Input (Reset Only) Manufacturing Options. Must be pulled-up. Must be externally pulled-up Input (Reset Only) User Defined Bootstrap: Usually used in conjuction with Module Detect to determine what interface to use for the inserted module. Can be read from BOOTSTRAP2 register 16 Zarlink Semiconductor Inc. Data Sheet Description ...
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... M[7:0]_TXEN (O) M[7:0]_TXEN (O) M[7:0]_CRS_DV (I) M[7:0]_DV (I) M[7:0]_TXD0 (O) M[7:0]_TXD0 (O) M[7:0]_TXD1 (O) M[7:0]_TXD1 (O) NC (O) M[7:0]_TXD2 (O) NC (O) M[7:0]_TXD3 (O) NC (D) M[7:0]_COL (I) NC (U) M[7:0]_TXCLK (IO) NC (U) M[7:0]_RXCLK (IO) 17 Zarlink Semiconductor Inc. Data Sheet GPSI Mode (ECR4Pn[4:3]='00') M[7:0]_RXD (I) NC (U) NC (U) NC (U) M[7:0]_TXEN (O) M[7:0]_CRS (I) M[7:0]_TXD (O) NC (O) NC (O) NC (O) M[7:0]_COL (I) M[7:0]_TXCLK (IO) M[7:0]_RXCLK (IO) ...
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... Module (ECR4P9[4:3]='11') (Bootstrap TSTOUT9=’1’) (U) M9_RXD0 (I) (U) M9_RXD1 (I) (U) M9_RXD2 (I) (U) M9_RXD3 (I) (U) M9_RXDV (I) (D) M9_CRS (I) (D) M9_COL (I) (U) M9_RXCLK (IO) (O) M9_TXD0 (O) (O) M9_TXD1 (O) (O) M9_TXD2 (O) (O) M9_TXD3 (O) (U) M9_TXEN (O) (U) REF_CLK (I) (U) M9_MTXCLK (I) 18 Zarlink Semiconductor Inc. Data Sheet ...
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... CPU_MII_RXD1 (I) NC (U) CPU_MII_RXD2 (I) NC (U) CPU_MII_RXD3 (I) NC (U) CPU_MII_RXCLK (O) NC (U) CPU_MII_RXDV (I) NC (U) NC (U) NC (U) NC (U) 19 Zarlink Semiconductor Inc. Data Sheet Serial Only (TSTOUT[3:1]=’011’ or ‘111’) SDA (IOU) (111 only) SCL (OU) (111 only) NC (U) STROBE (IU) DATAOUT (O) DATAIN (IU) P_INT# (O) NC (U) NC (U) NC (U) ...
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... To enable SSI-only lightly managed mode, pulled-down TSTOUT[3]. To enable SSI+MII lightly managed mode, pulled-down TSTOUT[3,1] ZL50409 Description TSTOUT[0] enables or disables the DEBOUNCE feature (refer to “Synchronous Serial Interface” on page 32) TSTOUT[6:4] selects the device ID Table 4 - Bootstrap Features 20 Zarlink Semiconductor Inc. Data Sheet 2 C EEPROM can be used to configure ...
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... No shared or per-class buffer pools • Per-port Defaults • Disable per-port fixed priority and drop precedence • Disable asynchronous flow control • Spanning Tree per-port state equal to forwarding • Don’t filter tagged/untagged VLAN frames ZL50409 21 Zarlink Semiconductor Inc. Data Sheet ...
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... DiffServ EF code support disabled • No VLAN ID hashing • Per-port Defaults • FE Ports - Link heart beat disabled • CPU Port - 100M/Full Duplex/Flow Control - 8-byte header padding - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers ZL50409 22 Zarlink Semiconductor Inc. Data Sheet ...
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... These eight ports are denoted as ports The PHY addresses for the PHY devices connected to the 8 RMAC ports has to be from 08h (port 0) to 0Fh (port 7). ZL50409 8 RMAC X 8 Frame Engine Search Engine Internal Memory Figure 2 - Functional Block Diagram 23 Zarlink Semiconductor Inc. Data Sheet Other Internal Memory Block ...
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... Management Module decodes the control frame and executes the functions requested by the CPU. This module is only active in managed mode. In unmanaged mode, no control frame is accepted by the device. ZL50409 MAC Port PHY Address 0x08 0x09 ... 0x0F NA 0x10 Table 5 - PHY Addresses 24 Zarlink Semiconductor Inc. Data Sheet ...
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... This feature is enabled via a bootstrap pin (TSTOUT12). It also requires some register configuration via the CPU interface. See Programming Timeout Reset application note, ZLAN-41, for more information. 2.8 JTAG An IEEE1149.1 compliant test interface is provided for boundary scan. ZL50409 25 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 3 on page 27 provides an overview of the 8/16-bit interface. Figure 4 on page 28 provides an overview of the SSI interface. Figure 5 on page 29 provides an overview of the SSI+MII interface. ZL50409 ISA Interface Serial 16-bit NA 8-bit NA NA Yes NA Yes NA Yes 26 Zarlink Semiconductor Inc. Data Sheet MII I² Yes Yes 2 C ...
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... CPU Frame Reg Status Reg Reg (Addr = 3) (Addr = 4) (Addr = 5) 8/16-bit Data Bus CPU frame Transmit CPU frame FIFO Receive FIFO Interrupt 27 Zarlink Semiconductor Inc. Data Sheet Control Control Command 2 Command 1 Reg Reg (Addr = 6) (Addr = 7) 8/16-bit Data Bus Control Control Control Command 1 Command 1 ...
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... Status Reg Reg (Addr = 3) (Addr = 4) (Addr = 5) 8/16-bit Data Bus 8/16-bit Data Bus CPU frame Transmit CPU frame FIFO Receive FIFO Interrupt 28 Zarlink Semiconductor Inc. Data Sheet Control Control Command 2 Command 1 Reg Reg (Addr = 6) (Addr = 7) Control Control Control Command 1 Command 1 Transmit Command 2 ...
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... Command/ Index Reg 0 Reg Status Reg (Addr = 0) (Addr = 2) (Addr = 4) 8-bit Data Bus Internal Registers Inderect Access Figure 5 - Overview of the SSI+MII Interface 29 Zarlink Semiconductor Inc. Data Sheet Interrupt INT Control Interrupt Control Command 2 Reg Command 1 Reg Reg (Addr = 5) (Addr = 6) (Addr = 7) 8/16-bit Data Bus ...
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... ZL50409 once the transmit FIFO of ZL50409 is no longer under-run • Follow the standard Ethernet transmission format. CPU will see transmit enable (TXEN) be asserted by ZL50409 and CPU can start receiving data. CPU will stop receiving data once TXEN is de-asserted by ZL50409. ZL50409 12 Bit Register Address 30 Zarlink Semiconductor Inc. Data Sheet 0 ...
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... The master IC generates the timing signals and terminates data transfer. Figure 6 depicts the data transfer format. The slave address is the memory address of the EEPROM. Refer to “ZL50409 Register Description” on page 61 for I²C address for each register. ZL50409 31 Zarlink Semiconductor Inc. Data Sheet ...
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... To reduce the number of signals required, the register address, command and data are shifted in serially through the DATAIN pin. STROBE- pin is used as the shift clock. DATAOUT pin is used as data return path. ZL50409 ACK DATA 1 (8bits) ACK DATA 2 32 Zarlink Semiconductor Inc. Data Sheet ACK DATA M ACK STOP ...
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... Figure 8 - Serial Interface Read Command Functional Timing ZL50409 ... D12 ADDR CMD DATA ID0 ID1 ID2 ADDR CMD Zarlink Semiconductor Inc. Data Sheet 2 Extra clocks after last transfer D13 D14 D15 DATA ... D12 D13 D14 D15 ...
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... When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. ...
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... In addition, VLAN information is used to select the correct set of destination ports for the frame (for multicast verify that the frame’s destination port is associated with the VLAN (for unicast). ZL50409 Instead of using the patent-pending Zarlink Semiconductor scheduling 35 Zarlink Semiconductor Inc. Data Sheet ...
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... For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem. ZL50409 36 Zarlink Semiconductor Inc. Data Sheet ...
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... In a logical port-based set up, a logical port provides the application information of the packet. Certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications, such as VoIP. ZL50409 37 Zarlink Semiconductor Inc. Data Sheet ...
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... ZL50409 Yes Fix Port Priority? Use Default port settings No Yes No No VLAN Tag? No Yes IP Frame? Use Logical Port? No Use logical port Figure 9 - Priority Classification Rule 38 Zarlink Semiconductor Inc. Data Sheet IP Frame? Yes No Use TOS Yes ...
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... IEEE 802.1Q frame and the Q-in-Q frame, where the provider VLAN tag is inserted in front of the IEEE 802.1Q tag. ZL50409 Destination Port Numbers Bit Map Table 7 - Port-Based VLAN Mapping 39 Zarlink Semiconductor Inc. Data Sheet … ...
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... See IP Multicast Switching application note, ZLAN-52, for more information. ZL50409 IEEE 802.1Q Tag VLAN VLAN TCI Type/Length (2 Bytes) (2 Byte) Provider Tag (P-VLAN) IEEE 802.1Q Tag VLAN VLAN TCI VLAN TCI Tag Protocol ID (2 Bytes) (2 Bytes) (0x8100) Figure 10 - Q-in-Q Tagged Ethernet Frame 40 Zarlink Semiconductor Inc. Data Sheet Data Type/Length Data (2 Byte) ...
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... The maximum buffer size can be increased from the standard 1518 bytes (1522 with VLAN tag bytes. This is done using BUF_LIMIT, and is enabled on a per port basis via bit [1] in ECR3Pn. See Buffer Allocation application note, ZLAN-47, for more information. ZL50409 41 Zarlink Semiconductor Inc. Data Sheet ...
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... MAC TxFIFO. When transmission is done, the port control module requests that the buffer be released. 6.2.6 TxDMA The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules. ZL50409 42 Zarlink Semiconductor Inc. Data Sheet ...
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... Apps: emails, file backups. Latency: < desired, but not critical. Drop: No drop if P1 not oversubscribed. Table 8 - Two-dimensional World Traffic 43 Zarlink Semiconductor Inc. Data Sheet High Drop Probability (high-drop) Apps: training video. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed; first P3 to drop otherwise ...
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... The percent can be programmed by the register RDRC0, RDRC1. All packets will be ZL50409 Px > WRED_L1 Px > WRED_L2 X% 100 Table 9 - WRED Logic Behaviour 44 Zarlink Semiconductor Inc. Data Sheet BM Reject 100% 100% ...
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... Another segment of the FDB reserves space for each of the 10 ports — 9 ports for Ethernet and one CPU port (port number 8). Each port has it’s own programmable source port reservation. These 10 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. ZL50409 45 Zarlink Semiconductor Inc. Data Sheet ...
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... The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. ZL50409 Temporary reservation pri1 pri2 pri3 Figure 11 - Buffer Partition Scheme 46 Zarlink Semiconductor Inc. Data Sheet Shared Pool (CPU) ...
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... Classes P2 and P1 correspond to an assured forwarding (AF) group of size 2. Finally for best effort (BE) class. Features of the ZL50409 that correspond to the requirements of their associated IETF classes are summarized in the table below. ZL50409 NM+EF AF0 AF1 47 Zarlink Semiconductor Inc. Data Sheet P0 BE ...
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... Random early discard, with programmable levels Service only when other queues are idle means that QoS not adversely affected Shaper for traffic on uplink port Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified as BE xx-xx-xx-xx-xx-xx 88-08 yy-yy 48 Zarlink Semiconductor Inc. Data Sheet 00-00-... CRC ...
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... Two ports from trunk group 0 will be removed based on the hash key. In this example, we assume port 0 and 1 are removed result, port 2,5 and 6 are the only outgoing ports for this multicast packet. ZL50409 49 Zarlink Semiconductor Inc. Data Sheet ...
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... A CPU packet is send to the port in test in Device A. The packet will be forwarded to the test port, external cable, the destination port in Device B, and loop back to itself, back to the cable and go back to Device A and the CPU. This way, the whole channel can be tested. CPU DEVICE A ZL50409 Figure 12 - Remote Loopback Test 50 Zarlink Semiconductor Inc. Data Sheet DEVICE B ...
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... TCK is a clock used for the JTAG port. The frequency on this clock can vary. Refer to “JTAG (IEEE 1149.1-2001)” on page 132 for the frequency range. ZL50409 Table 12 - SCLK Speed Requirements 51 Zarlink Semiconductor Inc. Data Sheet Minimum SCLK speed required 50 MHz ...
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... M_CLK/20 for 10M mode. M_CLK needs 50MHz clock in this mode. If the MMAC port is configured in Reverse MII mode, RXCLK is generated from REF_CLK and is equal to REF_CLK/2 for 100M mode (no support for 10M Reverse MII mode). REF_CLK needs MHz clock in this mode. ZL50409 52 Zarlink Semiconductor Inc. Data Sheet ...
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... Frames with Length of 64 Bytes B[12] 8-L Jabber Frames B[13] 8-U Frames with Length Between 65-127 Bytes B[14] 9-L Oversize Frames B[15] 9-U Frames with Length Between 128-255 Bytes B[16] A-l B[17] A-u Frames with Length Between 256-511 Bytes B[18] B-l Frames with Length Between 512-1023 Bytes Frames with Length Between 1024-1528 Bytes B[19] B-u ZL50409 53 Zarlink Semiconductor Inc. Data Sheet 0 ...
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... Late Collision B[29] F-U Notation: X-Y Address in the contain memory X: Size and bits for the counter Y: D Word counter d: 24 bits counter bit [23: bits counter bit [31:24 bits counter bit [23:16] U1: 16 bits counter bit [15: bits counter bit [31:16] u: ZL50409 54 Zarlink Semiconductor Inc. Data Sheet ...
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... BUF_LIMIT if enabled for this port) > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) 55 Zarlink Semiconductor Inc. Data Sheet ...
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... VLAN Tagged) (> BUF_LIMIT if enabled for this port) don’t care don’t care < 10 bytes don’t care don’t care > 10 bytes, < 64 bytes don’t care don’t care any size any size 56 Zarlink Semiconductor Inc. Data Sheet ...
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... InDiscards Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process. 11.3.1.4 DelayExceededDiscards Counts number of frames discarded due to excessive transmit delay through the bridge. 11.3.1.5 MtuExceededDiscards Counts number of frames discarded due to excessive size. ZL50409 > Jabber 57 Zarlink Semiconductor Inc. Data Sheet ...
Page 58
... UndersizePkts Counts number of frames received with size less than 64 bytes. Frame size: No FCS error No framing error No collisions ZL50409 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) < 64 bytes, 58 Zarlink Semiconductor Inc. Data Sheet ...
Page 59
... BUF_LIMIT if enabled for this port) don’t care don’t care < 64 bytes don’t care > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) (> BUF_LIMIT if enabled for this port) don’t care any size 59 Zarlink Semiconductor Inc. Data Sheet ...
Page 60
... We also have two counters, one for unicast frames sent, and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called “frame send fail.” This keeps track of FIFO under-runs, late collisions, and collisions that have occurred 16 times. ZL50409 60 Zarlink Semiconductor Inc. Data Sheet ...
Page 61
... Description (Hex) 000+2n 001+2n 080+2n 081+2n 036 037 100 101 102+4n 103+4n 105+4n 170 200+n 208+4n 209+4n 20A+4n 20B+4n 228+2n Table 13 - Register Description 61 Zarlink Semiconductor Inc. Data Sheet I²C R/W Addr Default Notes (Hex) R/W 000+n 0C0 R/W 00A+n 000 R/W 014+n 000 R/W 01E+n 018 R/W NA ...
Page 62
... R/W 310+n R/W 323 R/W 324 RO 325 R/W 326 R/W 327 R/W 328 R/W 329 R/W 330-336 R/W 337 RO 338-339 RO 33A-33E R/W 33F R/W 400 R/W 401 R/W 403 R/W 62 Zarlink Semiconductor Inc. Data Sheet I²C Addr Default Notes (Hex) NA 0FF NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 (n=0..4) NA 000 000 NA 000 NA 000 ...
Page 63
... R/W 531 R/W 532 R/W 533 R/W 540 R/W 541 R/W 542 R/W 543 R/W 550+n R/W 558 R/W 560 R/W 561 R/W 562 R/W 63 Zarlink Semiconductor Inc. Data Sheet I²C Addr Default Notes (Hex) 04B 000 068 006 069 006 NA 003 090 000 091 000 NA 000 074 000 075 000 076 000 ...
Page 64
... R/W 594 R/W 595 R/W 5A0 R/W 5A1 R/W 5A2 R/W 5A3 R/W 5A4 R/W 600 R/W 601 R/W 602 R/W 603 R/W 604 R/W 64 Zarlink Semiconductor Inc. Data Sheet I²C Addr Default Notes (Hex) 0AB 000 0AC 000 0AD 000 092+n 000 (n=0..7) 09A+n 000 0A2 000 0A3 000 0A4 000 0A5 000 0A6 ...
Page 65
... R/W 60B R/W 610 R/W 611 R/W 612 R/W 613 R/W 614 R/W 620 R/W 621 R/W 622 R/W 700 R/W 701 R/W 702 R/W 703 R/W 704 R/W 705 R/W 65 Zarlink Semiconductor Inc. Data Sheet I²C Addr Default Notes (Hex) NA 000 NA 000 000 NA 002 0FF 000 NA 000 NA 000 NA 000 NA 000 NA 000 0BF 000 ...
Page 66
... R/W 708 R/W 709 R/W 70A R/W 70B R/W 70C R/W 710 R/W 711 R/W 800+n R/W 820+n R/W 840+n R/W 848 R/W 849 R/W 860+n R/W 868 R/W 869 R/W 66 Zarlink Semiconductor Inc. Data Sheet I²C Addr Default Notes (Hex) NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 04C+n 000 (n=0..9) 05E+n 000 06A+n 006 ‘d1536/16 =‘ ...
Page 67
... EA0+n RO EA8 RO EA9 RO EAA RO EAB RO EAC RO EAD R/W EB0+n R/W EBA R/W EBB R/O EBC R/O EBD R/W EC0 R/W EC1 R/W 67 Zarlink Semiconductor Inc. Data Sheet I²C Addr Default Notes (Hex) 078-08F 000 (n=0..39 000 NA 001 0F6 000 0F7 000 0F8 000 0F9 000 0FA 000 ...
Page 68
... In 8-bit mode: Address bits [15:8] ZL50409 CPU Addr Description (Hex) EC2 EC3 EC4 EC5 EC6 EC7 EC8 EC9 ECA ECB ECC ECD F00 F01 F02 F03 F04 FFF 68 Zarlink Semiconductor Inc. Data Sheet I²C R/W Addr Default Notes (Hex) R/W NA 000 R/W NA 000 R/W NA 000 R/W NA 000 R/W NA 006 R/W ...
Page 69
... CPU has to wait until this bit read a new control command Bit [3]: Transmit FIFO has data for CPU to read (TXFIFO_RDY) Bit [4]: Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK) Bit [5]: Transmit FIFO End Of Frame (TXFIFO_EOF) Bits [7:6]: Reserved ZL50409 69 Zarlink Semiconductor Inc. Data Sheet ...
Page 70
... Accessed by CPU and I²C (R/W) Port 0 – 7 & 9: (RMAC & MMAC Ports) Bit [0] Flow Control 0 - Enable (Default Disable Bit [1] Duplex Mode 0 - Full Duplex (Default Half Duplex - Only in 10/100 mode Bit [2] Speed 0 - 100 Mbps (Default Mbps ZL50409 70 Zarlink Semiconductor Inc. Data Sheet ...
Page 71
... Must be ‘1’. ZL50409 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) 71 Zarlink Semiconductor Inc. Data Sheet ...
Page 72
... Do not change VLAN tag. This overrides PVMAPnn_3 bit [2]. If this bit is set, no tag will be replaced nor removed. 0: Disable (Default) 1: Enable ZL50409 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) 72 Zarlink Semiconductor Inc. Data Sheet ...
Page 73
... Bit [2]: Enable pad frame to 64B when transmitted 0: Allow padding to 64B (Default) 1: Disable Bit [3]: Enable compress preamble 0: Send standard preamble (Default) 1: Only one byte preamble+SFD Bits [6:4] Number of bytes removed from the Inter-Frame Gap (IFG). (Default 0x0) ZL50409 73 Zarlink Semiconductor Inc. Data Sheet ...
Page 74
... MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit [6]: Link Heart Beat Receive 0: Disable (Default). Also clears all MAC LHB status. 1: Enable Bit [7]: Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing. ZL50409 74 Zarlink Semiconductor Inc. Data Sheet ...
Page 75
... Reserved Bit [1]: Enable RXCLK output. Active high 0: Disable (Default) 1: M9_RXCLK pin becomes output in MII mode Note: To configure port 9 with the device providing the interface clocks, you need to tie M9_RXCLK to M9_MTXCLK externally as M9_MTXCLK is not a bidirectional clock. ZL50409 75 Zarlink Semiconductor Inc. Data Sheet ...
Page 76
... CPU Address:h036 Accessed by CPU (R/W) Bits [6:0]: Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40) Bit [7]: Reserved 12.3.1.6 FCC – Flow Control Grant Period CPU Address:h037 Accessed by CPU (R/W) Bits [2:0]: Flow Control Grant Period (Default 0x3) Bits [7:3]: Reserved ZL50409 76 Zarlink Semiconductor Inc. Data Sheet ...
Page 77
... PVMAP00_1 – Port 0 Configuration Register 1 I²C Address h34, CPU Address:h103 Accessed by CPU and I²C (R/W) In Port based VLAN Mode Bits [1:0]: VLAN Mask for ports (Default 0x3) Bits [7:2]: Reserved (Default 0x3F) In Tag based VLAN Mode Bits [3:0]: PVID [11:8] (Default is 0xF) ZL50409 77 Zarlink Semiconductor Inc. Data Sheet ...
Page 78
... Force untag out (VLAN tagging is based on IEEE 802.1Q rule Disable (Default Force untagged output. All packets transmitted from this port are untagged. This bit is used when this port is connected to legacy equipment that does not support VLAN tagging. ZL50409 78 Zarlink Semiconductor Inc. Data Sheet ...
Page 79
... Same function as SE_OPMODE bit [7]. Either bit can enable the function; both need to be turned off to disable the feature. Bit [2]: Disable dropping of frames with destination MAC addresses 01-80-C2-00-00-01 to 0x01-80-C2-00-00-0F. 0: Drop all frames in this range (Default) 1: Disable dropping of frames in this range ZL50409 79 Zarlink Semiconductor Inc. Data Sheet ...
Page 80
... Trunk Group – eight RMAC ports can be selected for each trunk group. 12.3.3.1 TRUNKn– Trunk Group 0~7 CPU Address:h200 trunk group) Accessed by CPU (R/W) Bit [7:0] Port 7-0 bit map of trunk n. (Default 0) ZL50409 TRUNK0 Zarlink Semiconductor Inc. Data Sheet ...
Page 81
... Any port not belonging to a trunk group should be programmed with 1. Ports belonging to the same trunk group should only have a single port set to “1” per entry. The port set to “1” is picked to transmit the multicast frame when the hash value is met. ZL50409 81 Zarlink Semiconductor Inc. Data Sheet ...
Page 82
... Use Source Port Number for hashing (Default) MULTICAST_HASH[7:1]-1 Reserved (Default 0x3) ZL50409 HASH0-1 HASH0-0 HASH1-1 HASH1-0 HASH2-1 HASH2-0 HASH3-1 HASH3-0 HASH4-1 HASH4-0 HASH5-1 HASH5-0 HASH6-1 HASH6-0 HASH7-1 HASH7 Zarlink Semiconductor Inc. Data Sheet ...
Page 83
... CPU Address:h303 Accessed by CPU (R/W) Bits [7:0]: Byte 3 (bits [31:24]) of the CPU MAC address (Default 0) 12.3.4.5 MAC4 – CPU MAC address byte 4 CPU Address:h304 Accessed by CPU (R/W) Bits [7:0]: Byte 4 (bits [39:32]) of the CPU MAC address (Default 0) ZL50409 MAC3 MAC2 MAC1 MAC0 83 Zarlink Semiconductor Inc. Data Sheet 0 (MC bit) ...
Page 84
... Reserved Bit [4]: Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic counter wraps around. Refer to hardware statistic counter for interrupt sources. Bit [5]: Port 1 link change mask Bit [6]: Port 1 module detect mask Bit [7] Reserved ZL50409 84 Zarlink Semiconductor Inc. Data Sheet ...
Page 85
... Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0). 12.3.4.11 RQSS – Receive Queue Status CPU Address:h324 Accessed by CPU (RO) CPU receive queue status Bits [3:0]: Unicast Queue not empty 0: Empty 1: Not Empty Bits [7:4]: Multicast Queue not empty ZL50409 85 Zarlink Semiconductor Inc. Data Sheet ...
Page 86
... Reserved Bits [6:4]: Bits [42:40] of Port 5 CPU MAC address Bit [7]: Reserved 12.3.4.15 MAC67 – Increment MAC port 6,7 address CPU Address:h328 Accessed by CPU (RW) Bits [2:0]: Bits [42:40] of Port 6 CPU MAC address Bit [3]: Reserved Bits [6:4]: Bits [42:40] of Port 7 CPU MAC address Bit [7]: Reserved ZL50409 86 Zarlink Semiconductor Inc. Data Sheet ...
Page 87
... CPU command queue status The command is under processing. Bit [0]: Insertion Fail (May be due to queue full, WRED or filtering) Bit [1]: 12.3.4.19 CPUGRNHDL0 - CPUGRNHDL1 – CPU Allocated Granule Pointer CPU Address:h338-339 Accessed by CPU, (RO) ZL50409 CQ4 CQ3 CQ2 15 0 CG1 CG0 87 Zarlink Semiconductor Inc. Data Sheet 0 CQ1 CQ0 ...
Page 88
... Used in conjuction with AGETIME_HIGH. The ZL50409 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bits [7:0]: Low byte of the MAC address aging timer (Default 0x5C) ZL50409 CR3 CR2 CR1 CR0 88 Zarlink Semiconductor Inc. Data Sheet 0 ...
Page 89
... Enable speed-up aging when MCT resource is low. (Default) 1 – Disable speed-up aging when MCT resource is low. Bit [7]: Slow Learning 0 – Learning is performed independent of search demand (Default) 1 – Enable slow learning. Learning is temporary disabled when search demand is high ZL50409 89 Zarlink Semiconductor Inc. Data Sheet ...
Page 90
... MCC – Multicast Congestion Control I²C Address h069, CPU Address: 511 Accessed by CPU and I²C (R/W) Bits [7:0]: In multiples of 16 granules (granularity). Used for triggering MC flow control when destination port’s multicast best effort queue reaches MCC threshold. (Default 0x6) ZL50409 90 Zarlink Semiconductor Inc. Data Sheet ...
Page 91
... See Programming QoS Registers application note, ZLAN-42, for more information 12.3.6.7 RDRC2 – WRED Rate Control 2 CPU Address 515 Accessed by CPU (R/W) Bits [3:0]: Corresponds to the frame drop percentage RB% for ingress rate control. Granularity 6.25%. Bits [7:4]: Corresponds to the frame drop percentage RA% for ingress rate control. Granularity 6.25%. ZL50409 91 Zarlink Semiconductor Inc. Data Sheet ...
Page 92
... ZL50409. When the packet goes out it carries the original priority. Bits [2:0]: Priority when the VLAN tag priority field is 0 (Default 0) Bits [5:3]: Priority when the VLAN tag priority field is 1 (Default 0) Bits [7:6]: Priority when the VLAN tag priority field is 2 (Default 0) ZL50409 92 Zarlink Semiconductor Inc. Data Sheet ...
Page 93
... Frame drop priority when VLAN Tag priority field is 4 (Default 0) Bit [5]: Frame drop priority when VLAN Tag priority field is 5 (Default 0) Bit [6]: Frame drop priority when VLAN Tag priority field is 6 (Default 0) Bit [7]: Frame drop priority when VLAN Tag priority field is 7 (Default 0) ZL50409 93 Zarlink Semiconductor Inc. Data Sheet ...
Page 94
... Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Frame drop priority when TOS field is 0 (Default 0) Bit [1]: Frame drop priority when TOS field is 1 (Default 0) Bit [2]: Frame drop priority when TOS field is 2 (Default 0) ZL50409 94 Zarlink Semiconductor Inc. Data Sheet ...
Page 95
... The ZL50409 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: • 23 • 512 • 6000 • 443 • 111 ZL50409 95 Zarlink Semiconductor Inc. Data Sheet ...
Page 96
... Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for Well known port 4 (111 for sun remote procedure call) Bits [7:4]: Priority setting, transmission + dropping, for Well known port 5 (22555 for IP Phone call setup) ZL50409 be programmed via WELL_KNOWN_PORT[7:0]_PRIORITY 96 Zarlink Semiconductor Inc. Data Sheet register. ...
Page 97
... Bit [3]: Enable Well Known Port 3 Force Discard Bit [4]: Enable Well Known Port 4 Force Discard Bit [5]: Enable Well Known Port 5 Force Discard Bit [6]: Enable Well Known Port 6 Force Discard Bit [7]: Enable Well Known Port 7 Force Discard ZL50409 97 Zarlink Semiconductor Inc. Data Sheet ...
Page 98
... I²C Address h0A4, CPU Address 592 Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for logic port 4 Bits [7:4]: Priority setting, transmission + dropping, for logic port 5 (Default 00) ZL50409 0 TCP/UDP Logic Port Low 0 TCP/UDP Logic Port High 98 Zarlink Semiconductor Inc. Data Sheet ...
Page 99
... Enable User Port 2 Force Discard Bit [3]: Enable User Port 3 Force Discard Bit [4]: Enable User Port 4 Force Discard Bit [5]: Enable User Port 5 Force Discard Bit [6]: Enable User Port 6 Force Discard Bit [7]: Enable User Port 7 Force Discard ZL50409 99 Zarlink Semiconductor Inc. Data Sheet ...
Page 100
... RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit [0]: Drop Priority (inclusive only) Bits [3:1] Transmit Priority (inclusive only) Bits [5:4] Reserved Bits [7: Filtering 01 - Exclusive Filtering (x<=RLOW or x>=RHIGH Inclusive Filtering (RLOW<x<RHIGH Invalid ZL50409 100 Zarlink Semiconductor Inc. Data Sheet ...
Page 101
... Accessed by CPU and I²C (R/W) Bit [0]: Statistic Counter 0 – Disable (Default) 1 – Enable (all ports) When statistic counter is enable, an interrupt control frame is generated to the CPU, every time a counter wraps around. This feature requires an external CPU. Bit [1]: 0 ZL50409 101 Zarlink Semiconductor Inc. Data Sheet ...
Page 102
... MII Command Data [7:0] Note : Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command. 12.3.7.5 MIIC1 – MII Command Register 1 CPU Address:h604 Accessed by CPU (R/W) Bits [7:0]: MII Command Data [15:8] ZL50409 102 Zarlink Semiconductor Inc. Data Sheet ...
Page 103
... MII command. Writing this register will initiate a serial management cycle to the MII management interface. 12.3.7.8 MIID0 – MII Data Register 0 CPU Address:h607 Accessed by CPU (RO) Bits [7:0]: MII Data [7:0] 12.3.7.9 MIID1 – MII Data Register 1 CPU Address:h608 Accessed by CPU (RO) Bits [7:0]: MII Data [15:8] ZL50409 103 Zarlink Semiconductor Inc. Data Sheet ...
Page 104
... Accessed by CPU and I²C (R/W) Bits [7:0]: Checksum content (Default 0) This register is used in unmanaged mode only. Before requesting that the ZL50409 updates the EEPROM device, the correct checksum needs to be calculated and written into this checksum register. ZL50409 104 Zarlink Semiconductor Inc. Data Sheet ...
Page 105
... I²C Address 0BF, CPU Address:h620 Accessed by CPU and I²C (R/W) Bits [7:0] FCB Base address bit 7:0 (Default 0) 12.3.7.17 FCB Base Address Register 1 I²C Address 0C0, CPU Address:h621 Accessed by CPU and I²C (R/W) Bits [7:0] FCB Base address bit 15:8 (Default 0x60) ZL50409 105 Zarlink Semiconductor Inc. Data Sheet ...
Page 106
... RMAC_MIRROR0 – RMAC Mirror 0 CPU Address 710 Accessed by CPU (R/W) Bits [2:0]: Source port to be mirrored ZL50409 DEST_MAC3 DEST_MAC2 DEST_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) SRC_MAC3 SRC_MAC2 SRC_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) 106 Zarlink Semiconductor Inc. Data Sheet DEST_MAC0 [7:0] (Default 00) SRC_MAC0 [7:0] (Default 00) ...
Page 107
... To disable this function, program U2MR to 0. (Default = 0) Bits [6:4]: Time Base for Unicast to Multicast, Multicast and Broadcast rate control of Port n: (Default = 000) 000 = 100us 001 = 200us 010 = 400us 011 = 800us 100 = 1.6ms 101 = 3.2ms 110 = 6.4ms 111 = 12.8ms Bit [7]: Reserved ZL50409 107 Zarlink Semiconductor Inc. Data Sheet ...
Page 108
... PTH100_CPU – Port CPU Threshold I²C Address h0CB, CPU Address 868 Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow control (Default 0x3) ZL50409 108 Zarlink Semiconductor Inc. Data Sheet ...
Page 109
... C Address h088, CPU Address 890 Address h089, CPU Address 891 Address h08A, CPU Address 892 Address h08B, CPU Address 893 Address h08C, CPU Address 894 Address h08D, CPU Address 895) 109 Zarlink Semiconductor Inc. Data Sheet ...
Page 110
... NOTE: Device Manufacturing test registers. 12.3.10.1 DTSRL – Test Output Selection CPU Address E00 Accessed by CPU (R/W) Test group selection for testout[7:0]. 12.3.10.2 DTSRM – Test Output Selection CPU Address E01 Accessed by CPU (R/W) Test group selection for testout[15:8]. ZL50409 110 Zarlink Semiconductor Inc. Data Sheet ...
Page 111
... TX FSM NOT idle for 5 sec Bit [0]: TX FIFO control NOT idle for 5 sec Bit [1]: RX SFD detection NOT idle for 5 sec Bit [2]: RXINF NOT idle for 5 sec Bit [3]: PTCTL NOT idle for 5 sec Bit [4]: ZL50409 23 15 BT2 BT1 111 Zarlink Semiconductor Inc. Data Sheet 0 BT0 ...
Page 112
... L1 WRED level Bit [5]: priority queue 1 reach L2 WRED level Bit [6]: priority queue 2 reach L1 WRED level Bit [7]: priority queue 2 reach L2 WRED level Bit [8]: priority queue 3 reach L1 WRED level Bit [9]: priority queue 3 reach L2 WRED level ZL50409 PQSTB PQSTA 112 Zarlink Semiconductor Inc. Data Sheet 0 ...
Page 113
... Priority 0 MC queue full Bit [11]: Priority 1 MC queue full Bit [12]: Priority 2 MC queue full Bit [13]: Priority 3 MC queue full Bits [15:14]: Reserved 12.3.10.10 CLASSQOSST CPU Address EAC Accessed by CPU (RO) Bit [0]: No share buffer Bit [1]: No class 1 buffer ZL50409 0 PQSTA 113 Zarlink Semiconductor Inc. Data Sheet ...
Page 114
... Force out XON flow control frame 12.3.10.13 QCTRL CPU Address EBA Accessed by CPU (R/W) Stop QM FSM at idle Bit [0]: Stop MCQ FSM at idle Bit [1]: Stop new granule grant to any source Bit [2]: Stop release granule from any source Bit [3]: Reserved Bits [7:4]: ZL50409 114 Zarlink Semiconductor Inc. Data Sheet ...
Page 115
... Note : Before CPU doing so, CPU should set QCTRL (CPU Address EBA) bit 2 and bit 3 to one. After reset the pools, CPU shall reprogram free granule link list (CPU address EC1, EC2, EC3, EC4, EC5, EC6). Then clear QCTRL (EBA). ZL50409 115 Zarlink Semiconductor Inc. Data Sheet ...
Page 116
... Fcb_number[7:0]. The total number of granules that CPU assigns. CPU address EC6 Accessed by CPU (R/W) Bits [6:0] Fcb_number[14:8]. The total number of granules that CPU assigns. Bit [7] Set 1 to write If CPU wants to write again, CPU has to clear bit 15 and then set bit 15. ZL50409 116 Zarlink Semiconductor Inc. Data Sheet ...
Page 117
... BM_RSLFF_INFO[5:0] CPU address EC8 Accessed by CPU (RO) Bits [7:0] Rls_head_ptr[7:0]. CPU address EC9 Accessed by CPU (RO) Bits [6:0] Rls_head_ptr[14:8]. Bit [7] Rls_tail_ptr[0] CPU address ECA Accessed by CPU (RO) Bits [7:0] Rls_tail_ptr[8:1] CPU address ECB Accessed by CPU (RO) Bits [5:0] Rls_tail_ptr[14:9] Bits [7:6] Rls_count[1:0] ZL50409 117 Zarlink Semiconductor Inc. Data Sheet ...
Page 118
... This bit is reserved in unmanaged mode. In managed mode, the CPU writes this bit with ‘1’ to indicate initialization is completed and ready to forward packets. The ‘0' to '1' transition will toggle TSTOUT[2] from low to high. Bits [7:5]: Reserved ZL50409 118 Zarlink Semiconductor Inc. Data Sheet ...
Page 119
... Port 5 Operating mode and Negotiation status - 5’b00110 - Port 6 Operating mode and Negotiation status - 5’b00111 - Port 7 Operating mode and Negotiation status - 5’b01000 - Port CPU Operating mode and Negotiation status - 5’b01001 - Port MMAC Operating mode and Negotiation status Bits [7:5]: Reserved ZL50409 119 Zarlink Semiconductor Inc. Data Sheet ...
Page 120
... Note: If Module Detect feature is disabled (bootstrap TSTOUT[9]=’0’), this bit will always be ‘1’. 12.3.11.6 DA – Dead or Alive Register CPU Address: hFFF Accessed by CPU (RO) Always return 8’ Indicate the CPU interface or serial port connection is good. Bits [7:0] Always return DA ZL50409 120 Zarlink Semiconductor Inc. Data Sheet ...
Page 121
... Functionality at or above these limits is not implied. 13.2 DC Electrical Characteristics V = 3.3 V +/- 10 1.8 V +/- 5% DD ZL50409 - +150 +125 C +2. +3. +1. + +85 C AMBIENT 121 Zarlink Semiconductor Inc. Data Sheet ...
Page 122
... Thermal resistance with 0 air flow ja Thermal resistance with 1 m/s air flow ja Thermal resistance with 2 m/s air flow ja Thermal resistance between junction and case jc ZL50409 Min. 2.4 2.0 < < OUT CC 122 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Unit 50 100 MHz 50 mA 180 ...
Page 123
... Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# assertion ZL50409 Tri-Stated R3 Inputs R2 Min. Typ RESETOUT# state is then determined by the external pull-up/down resistor Bootstrap pins sampled on rising edge of RESIN 123 Zarlink Semiconductor Inc. Data Sheet Outputs Note: ...
Page 124
... Max. Min. Max 124 Zarlink Semiconductor Inc. Data Sheet Activ e Tim ATA1 Refer to Figure 14 P_A and P_CS# to falling edge of P_WE# At least 2 SCLK cycles P_A and P_CS# to rising edge of P_WE# ...
Page 125
... Inv alid tim e (SCLK=100 Mhz) (SCLK=50 Mhz) Min. Max. Min 125 Zarlink Semiconductor Inc. Data Sheet Activ e Tim ATA1 Refer to Figure 15 Max. P_A and P_CS# to falling edge of P_RD# At least 2 SCLK cycles ...
Page 126
... M[7:0]_CRS_DV Input Hold Time M6 M[7:0]_TXEN Output Delay Time M7 M[7:0]_TXD[1:0] Output Delay Time ZL50409 M_CLK M6-max M6-min Mn_TXEN M7-max M7-min Mn_TXD[1:0] M_CLK M2 Mn_RXD M3 M4 Mn_CRS_DV M5 Parameter Min. (ns) 126 Zarlink Semiconductor Inc. Data Sheet M_CLK=50 MHz Note: Max. (ns ...
Page 127
... Mn_TXD[3:0] Output Delay Time ZL50409 Mn_TXCLK MM6-max MM6-min Mn_TXEN MM7-max MM7-min Mn _TXD[3:0] Mn_RXCLK MM2 Mn_RXD[3: MM4 Mn_CRS_DV MM 5 Min. (ns 127 Zarlink Semiconductor Inc. Data Sheet 25 MHz Note: Max. (ns) CPU MII Interface CPU MII Interface ...
Page 128
... M[7:0]_TXEN Output Delay Time SM7 M[7:0]_TXD Output Delay Time ZL50409 Mn_ TXCLK SM6-max SM6-min Mn_TXEN SM7-max SM7-min Mn_TXD Mn_RXCLK SM2 Mn_RXD SM3 SM4 Mn_CRS_DV SM5 Parameter Min. (ns) 128 Zarlink Semiconductor Inc. Data Sheet 10 MHz Note: Max. (ns ...
Page 129
... MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time ZL50409 MDC D1 D2 MDIO MDC D3-max D3-min MDIO Figure 23 - MDIO Output Delay Timing MDC=500 KHz Parameter Min. (ns 129 Zarlink Semiconductor Inc. Data Sheet Note: Max. (ns ...
Page 130
... Open Drain Output. Low to High transistor is controlled by external pullup resistor. ZL50409 SCL S1 SDA Figure 24 - I²C Input Setup Timing SCL S3-max S3-min SDA Figure 25 - I²C Output Delay Timing SCL=50 KHz Parameter Min. (ns usec 130 Zarlink Semiconductor Inc. Data Sheet S2 Note: Max. (ns) 6 usec ...
Page 131
... STROBE high time ZL50409 Figure 26 - Serial Interface Setup Timing D3-max D3-min Parameter Min. (ns 131 Zarlink Semiconductor Inc. Data Sheet D5 D2 Max. (ns) Note: Debounce on Debounce off 100 pf L Debounce on Debounce off Debounce on Debounce off ...
Page 132
... TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK to TDO data valid ZL50409 J1 J2 Figure 28 - JTAG Timing Diagram Min. Typ. Max 132 Zarlink Semiconductor Inc. Data Sheet Units Note: MHz TRST is an asynchronous signal ...
Page 133
... Clarified that only bit [7] is not self-clearing • Updated CPU timing diagrams to clarify timing 14.5 November 2004 • Added section “Default Switch Configuration and Initialization Sequence” on page 21 • Updated CPU timing diagrams to clarify P_A timing ZL50409 133 Zarlink Semiconductor Inc. Data Sheet ...
Page 134
... TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN 14Nov02 DATE APPRD. BOTTOM VIEW b Previous package codes Dimension MIN MAX 1. 0.30 0.50 0.53 REF A2 D 16.90 17.10 E 16.90 17.10 b 0.40 0.60 e 1.00 N 208 Conforms to JEDEC MO-192 Package Code ...
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