CY7C09349 Cypress Semiconductor Corporation., CY7C09349 Datasheet
CY7C09349
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CY7C09349 Summary of contents
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... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — organization (CY7C09349) — organization (CY7C09359) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100-MHz cycle time • ...
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... Functional Description The CY7C09349 and CY7C09359 are high-speed synchro- nous CMOS 4K and dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. control, address, and data lines allow for minimal set-up and hold times ...
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... Typical Operating Current I (mA) CC Typical Standby Current for I (mA) SB1 (Both Ports TTL Level) Typical Standby Current for I (mA) SB3 (Both Ports CMOS Level) Note: 4. This pin is NC for CY7C09349. PRELIMINARY 100-Pin TQFP (Top View ...
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... For read operations both Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Shaded areas contain advance information. 4 CY7C09349 CY7C09359 AND CE must be asserted –I/O 8/9L 15/17L Ambient Temperature + – ...
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... Test Conditions MHz 5.0V CC AND CE must be asserted to their active states ( CY7C09349 CY7C09359 -9 -12 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0.8 10 –10 10 –10 10 215 360 195 300 240 410 225 375 ...
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... OUTPUT (b) Thévenin Equivalent (Load 1) [6] 3.0V GND 1. Capacitance (pF) (b) Load Derating Curve 6 CY7C09349 CY7C09359 893 OUTPUT 347 = 1.4V (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ including scope and jig) ALL INPUT PULSES ...
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... CY7C09349 CY7C09359 CY7C09349 CY7C09359 -7 -9 -12 Max. Min. Max. Min. Max ...
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... A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only CY7C09349 CY7C09359 n+3 t CKHZ Q Q n+1 n OHZ OLZ ...
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... [14, 15, 16, 17] NO MATCH t CD1 MATCH t CWDD VALID , R/W, CNTEN, and CNTRST = for the left port, which is being written to CY7C09349 CY7C09359 CD2 CKHZ CKHZ CKLZ ...
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... n+1 n CD2 CKHZ Q n READ NO OPERATION [11, 18, 19, 20 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH 10 CY7C09349 CY7C09359 A A n+3 n CD2 CKLZ WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ Q n+3 ...
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... n+1 n CD1 Q n CKHZ NO READ OPERATION [9, 11, 18, 19 n OHZ READ WRITE 11 CY7C09349 CY7C09359 n+2 n+3 n n+2 t CD1 Q n CKLZ DC WRITE READ A A n+3 n+4 n+5 n CD1 Q n CKLZ DC READ t CD1 t CD1 ...
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... R/W and CNTRST = PRELIMINARY [21] t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER [21 n+1 READ WITH COUNTER . IH 12 CY7C09349 CY7C09359 t HAD t HCN Q n+2 READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+3 n+2 READ COUNTER HOLD WITH COUNTER Q n+3 ...
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... CE and CNTRST = 23. The “Internal Address” is equal to the “External Address” when ADS = V PRELIMINARY A n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = CY7C09349 CY7C09359 [22, 23 n+2 n n+3 n+4 WRITE WITH COUNTER . IH n+4 ...
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... UB, and 25. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. PRELIMINARY WRITE READ ADDRESS 0 ADDRESS 0 14 CY7C09349 CY7C09359 n READ READ ADDRESS 1 ...
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... L D Reset out( Load out( Hold out( Increment out(n+ CY7C09349 CY7C09359 Operation 17 [29] Deselected [29] Deselected Write [29] Read Outputs Disabled Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation ...
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... Ordering Information 4K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09349-6AC 7.5 CY7C09349-7AC CY7C09349-7AI 9 CY7C09349-9AC CY7C09349-9AI 12 CY7C09349-12AC CY7C09349-12AI 8K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09359-6AC 7.5 CY7C09359-7AC CY7C09359-7AI 9 CY7C09359-9AC CY7C09359-9AI 12 CY7C09359-12AC CY7C09359-12AI Shaded areas contain advance information. Document #: 38–00672–C PRELIMINARY Package Name ...
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... Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 PRELIMINARY 17 CY7C09349 CY7C09359 51-85048-B ...
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... POR circuit is at fault. Applicable devices—All speed/package/temperature combi- nations of the following: • CY7C09349 • CY7C09359 Cypress design change—Cypress design team has identified the root cause. A permanent circuit change and die revision will be available beginning in October and will be identified by the letter “ ...