ISPLSI2128-80LQ Lattice Semiconductor Corp., ISPLSI2128-80LQ Datasheet

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ISPLSI2128-80LQ

Manufacturer Part Number
ISPLSI2128-80LQ
Description
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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ISPLSI2128-80LQ
Manufacturer:
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Manufacturer:
LATTICE
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Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2128_10
• ENHANCEMENTS
• HIGH DENSITY PROGRAMMABLE LOGIC
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
Features
— ispLSI 2128A is Fully Form and Function Compatible
— ispLSI 2128A is Built on an Advanced 0.35 Micron
— 6000 PLD Gates
— 128 I/O Pins, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
— Lead-Free Package Options
to the ispLSI 2128, with Identical Timing
Specifcations and Packaging
E
Machines, Address Decoders, etc.
f
t
Market and Improved Product Quality
Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
max = 100 MHz Maximum Operating Frequency
pd = 10 ns Propagation Delay
2
CMOS
®
Technology
2
CMOS
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 2128 and 2128A are High Density Program-
mable Logic Devices. The devices contains128 Registers,
128 Universal I/O pins, eight Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2128 and 2128A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2128 and 2128A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. D7
(Figure 1). There are a total of 32 GLBs in the ispLSI 2128
and 2128A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Description
A0
A1
A2
A3
A4
A5
A6
A7
D7
Output Routing Pool (ORP)
B0
Output Routing Pool (ORP)
D6
B1
ispLSI
Global Routing Pool (GRP)
D5
B2
D4
B3
Logic
Array
Output Routing Pool (ORP)
D3
B4
Output Routing Pool (ORP)
D
D
D
D
D2
B5
®
Q
Q
Q
Q
2128/A
D1
B6
GLB
D0
B7
August 2006
C7
C6
C5
C4
C3
C2
C1
C0
0139(9A)/2128

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ISPLSI2128-80LQ Summary of contents

Page 1

... Interconnectivity — Lead-Free Package Options Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...

Page 2

Functional Block Diagram Figure 1. ispLSI 2128/A Functional Block Diagram RESET GOE 0 GOE 1 Megablock D7 I I/O 1 I/O 2 I I/O 5 I/O 6 I/O 7 I ...

Page 3

Absolute Maximum Ratings Supply Voltage V ...................................-0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C ...

Page 4

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION R1 A ...

Page 5

External Timing Parameters 4 TEST 2 PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f max (Ext.) – ...

Page 6

Internal Timing Parameters 2 PARAMETER # Inputs Input Buffer Delay t 21 Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay 4ptbpc Product Term ...

Page 7

Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE0 Derivations of su, h and co from the Product Term Clock Logic ...

Page 8

Power Consumption Power consumption in the ispLSI 2128 and 2128A de- vices depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax I ...

Page 9

Pin Description PQFP/MQFP NAME PIN NUMBERS I I/O 4 26, 28, 29, 25, I I/O 9 32, 33, 34, 35, I I/O 14 37, 38, 39, 40, I I/O 19 46, 42, ...

Page 10

Pin Configuration ispLSI 2128/A 160-Pin PQFP Pinout Diagram 1 GND 2 I/O 114 3 I/O 115 I/O 116 4 5 I/O 117 6 I/O 118 7 I/O 119 8 I/O 120 I/O 121 9 10 GND I/O 122 11 12 ...

Page 11

Pin Configuration ispLSI 2128/A 176-Pin TQFP Pinout Diagram 1 GND 2 I/O 114 3 I/O 115 I/O 116 4 5 I/O 117 I/O 118 6 7 I/O 119 8 I/O 120 9 I/O 121 GND 11 12 ...

Page 12

Part Number Description ispLSI XXXXX XXX X X Device Family Device Number 1 2128 2128A Speed f 100 = 100 MHz max MHz max 1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory. ispLSI ...

Page 13

Ordering Information (Cont.) Lead-Free Packaging ...

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