K4T56083QF-GCCC Samsung, K4T56083QF-GCCC Datasheet
K4T56083QF-GCCC
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K4T56083QF-GCCC Summary of contents
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F-die DDR2 SDRAM 256Mb F-die DDR2 SDRAM Specification Version 1.5 February 2005 Page DDR2 SDRAM Rev. 1.5 Feb. 2005 ...
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F-die DDR2 SDRAM Contents 0. Ordering Information 1. Key Feature 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pintout & Mechnical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & ...
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... Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2 SDRAM Device Operation & Timing Diagram” DDR2-533 4-4-4 DDR2-400 3-3-3 K4T56043QF-GCD5 K4T56043QF-GCCC K4T56043QF-ZCD5 K4T56043QF-ZCCC K4T56083QF-GCD5 K4T56083QF-GCCC K4T56083QF-ZCD5 K4T56083QF-ZCCC DDR2-533 DDR2-400 Units 4-4-4 3-3-3 4 ...
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F-die DDR2 SDRAM 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pinout x4 package pinout (Top View) : 60ball FBGA Package 1 VDD NC VDDQ NC VDDL NC VSS VDD Notes: 1. Pin B3 has identical capacitance as pin ...
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F-die DDR2 SDRAM x8 package pinout (Top View) : 60ball FBGA Package 1 VDD DQ6 VDDQ DQ4 VDDL NC VSS VDD Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, ...
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F-die DDR2 SDRAM FBGA Package Dimension(x4/x8 60- 0.45r ‡ 0.05 ‡0.2 #A1 11.00 r 0.10 6.40 0.80 1. ...
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F-die DDR2 SDRAM 2.2 Input/Output Functional Description Symbol Type Clock: CK and CK are differential clock inputs. All address and control input signals are sampled CK, CK Input on the crossing of the positive edge of CK and negative ...
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F-die DDR2 SDRAM 2.3 256Mb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 512Mb Configuration # of Bank Bank Address Auto ...
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F-die DDR2 SDRAM 3. Absolute Maximum DC Ratings Symbol Parameter VDD Voltage on VDD pin relative to Vss VDDQ Voltage on VDDQ pin relative to Vss VDDL Voltage on VDDL pin relative to Vss V V Voltage on any ...
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F-die DDR2 SDRAM Operating Temperature Condition Symbol Parameter TOPER Operating Temperature 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard ...
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F-die DDR2 SDRAM Differential input AC logic Level Symbol Parameter V (AC differential input voltage V (AC differential cross point voltage Notes (AC) specifies the input differential voltage |V ID LDQS or UDQS) ...
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F-die DDR2 SDRAM OCD default characteristics Description Parameter Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Sout Notes: 1. Absolute Specifications (0° Impedance measurement condition for output source dc ...
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F-die DDR2 SDRAM IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Proposed Conditions IDD0 Operating one bank active-precharge current CK(IDD), t ...
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F-die DDR2 SDRAM Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of ...
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... D5(DDR2-533@CL=4) CC(DDR2-400@CL=3) 100 95 110 100 160 125 150 125 165 160 5 5 250 245 32Mx8(K4T56083QF) 100 95 110 100 175 135 160 130 165 160 5 5 255 255 Page ...
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F-die DDR2 SDRAM Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, ...
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F-die DDR2 SDRAM Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Symbol Parameter DDR2-667 min DQ output access time tAC -450 from CK/CK DQS output access tDQSCK -400 time from ...
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F-die DDR2 SDRAM Symbol Parameter DDR2-667 min Mode register set tMRD 2 command cycle time Write postamble tWPST 0.4 Write preamble tWPRE 0.35 Address and control tIH(base) 275 input hold time Address and control tIS(base) 200 input setup time ...
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F-die DDR2 SDRAM Symbol Parameter DDR2-667 min Exit active power down tXARDS read command (slow exit, lower power) CKE minimum pulse t CKE 3 width (high and low pulse width) ODT turn-on delay t 2 ...
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F-die DDR2 SDRAM General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for ...
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F-die DDR2 SDRAM 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized ...
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F-die DDR2 SDRAM Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is ...
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F-die DDR2 SDRAM 18. tIS and tIH (input setup and hold) derating. 2.0 V/ns 'tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 Com- 0.9 -11 mand/Ad- dress Slew 0.8 -25 rate 0.7 ...
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F-die DDR2 SDRAM For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example: tIS ...
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F-die DDR2 SDRAM culation is consistent. These notes are referenced in the “Timing parameters by speed grade” tables for DDR2-400/533/667 and DDR2-800. tHZ tRPST end point T2 T1 tHZ,tRPST = 2*T1-T2 end point 29. Input waveform timing with differential ...
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F-die DDR2 SDRAM 31. Input waveform timing is referenced from the input signal crossing at the V for a falling signal applied to the device under test. 32. Input waveform timing is referenced from the input signal crossing at ...
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F-die DDR2 SDRAM Revision History Version 1.0 (Jan. 2004) - Initial Release Version 1.1 (Jun. 2004) - Added Lead-Free part number in ordering information. - Changed IDD2P - Corrected Typo Version 1.2 (Aug. 2004) - Corrected the part number ...