K6F4016R4E-EF70 Samsung, K6F4016R4E-EF70 Datasheet
K6F4016R4E-EF70
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K6F4016R4E-EF70 Summary of contents
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... K6F4016R4E Family Document Title 256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial draft 1.0 Finalize The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products ...
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... SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice GENERAL DESCRIPTION The K6F4016R4E families are fabricated by SAMSUNG s advanced full CMOS process technology. The families support industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current ...
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... K6F4016R4E Family PRODUCT LIST Part Name K6F4016R4E-EF70 K6F4016R4E-EF85 FUNCTIONAL DESCRIPTION means don t care. (Must be low or high state) ...
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... K6F4016R4E Family RECOMMENDED DC OPERATING CONDITIONS Item Supply voltage Ground Input high voltage Input low voltage Note =- otherwise specified Overshoot: Vcc+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. ...
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... K6F4016R4E Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0 -0.2V CC Input rising and falling time: 5ns Input and output reference voltage: 0.9V Output load (See right 100pF+1TTL 30pF+1TTL L AC CHARACTERISTICS (T =- Vcc=1.65~2.2V) A Parameter List ...
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... K6F4016R4E Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address CS UB Data out High-Z NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6F4016R4E Family TIMING WAVEFORM OF WRITE CYCLE(1) Address CS UB Data in High-Z Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS UB Data in Data out (WE Controlled CW( WP(1) t AS( WHZ (CS Controlled AS(3) CW( WP( Data Valid ...
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... K6F4016R4E Family TIMING WAVEFORM OF WRITE CYCLE(3) Address CS UB Data in Data out High-Z NOTES (WRITE CYCLE wri e occurs during the overlap low CS and low WE. A write begins when CS goes low and WE goes low with asserting for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi- tion when CS goes high and WE goes high ...
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... K6F4016R4E Family PACKAGE DIMENSION 48 TAPE BALL GRID ARRAY(0.75mm ball pitch) Top View B #A1 Side View D C Min Typ A - 0.75 B 5.90 6. 3.75 C 6.90 7. 5.25 D 0.40 0.45 E 0.80 0. 0.55 E2 0.30 0. Bottom View Max - Notes. 6.10 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ ...