K7P801866B-HC25 Samsung, K7P801866B-HC25 Datasheet
K7P801866B-HC25
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K7P801866B-HC25 Summary of contents
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... K7P803666B K7P801866B Document Title 256Kx36 & 512Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Initial Document. Rev. 0 tolerance changed from 10% to 15% Rev. 0 changed to support wide range from 1.4V to 2.0V DDQ Rev. 0.3 - Functional Block diagram changed. - Absolute Maximum ratings VDDQ changed from 3.13V to 2.825V - Recommended DC Operating Conditions for V from Min 0 ...
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... Read Protocol Mode Pins ( Asynchronous Output Enable 256Kx36 & 512Kx18 SRAM Organization K7P803666B-HC33 256Kx36 K7P803666B-HC30 K7P803666B-HC25 K7P801866B-HC33 512Kx18 K7P801866B-HC30 K7P801866B-HC25 2:1 Dec. MUX Pin Name ZZ Asynchronous Power Down ZQ Output Driver Impedance Control TCK JTAG Test Clock TMS ...
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... V V DDQ DD K DQd DQd 1 L DQd DQd DQd DDQ N DQd DQd 6 P DQd DQd TMS DDQ K7P801866B(512Kx18 DDQ DQb DQb DDQ G NC DQb H DQb ...
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... FUNCTION DESCRIPTION The K7P803666B and K7P801866B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 262,144 words by 36 bits for K7P803666B and 524,288 words by 18 bits for K7P801866B, fabricated using Samsung's advanced CMOS technology. Single differential HSTL level K clocks are used to initiate read/write operation and all internal operations are self-timed. At the rising edge of K clock, Addresses, Write Enables, Synchronous Select and Data Ins are registered internally ...
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... K7P803666B K7P801866B TRUTH TABLE SWa NOTE : K & K are complementary ABSOLUTE MAXIMUM RATINGS Parameter ...
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... K7P803666B K7P801866B PIN CAPACITANCE Parameter Input Capacitance Data Output Capacitance NOTE : Periodically sampled and not 100% tested.(T DC CHARACTERISTICS Parameter Average Power Supply Operating Current-x36 ( & SS Average Power Supply Operating Current-x18 ( & SS Power Supply Standby Current ...
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... K7P803666B K7P801866B AC TEST CONDITIONS ( Parameter Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Input Reference Level Input Rise/Fall Time Input and Out Timing Reference Level Clock Input Timing Reference Level NOTE : Parameters are tested with RQ=250 and V ...
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... K7P803666B K7P801866B TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low KHKH t t AVKH KHAX SAn SVKH KHSX SS SW SWx t KHQV Q DQn NOTE the input data written in memory location the output data read from the write data buffer(not from the cell array result of address A 4 last write cycle address ...
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... K7P803666B K7P801866B TIMING WAVEFORMS OF STANDBY CYCLES KHKH SAn SWx ZZ t KHQV DQn Q 256Kx36 & 512Kx18 SRAM ZZE ZZR t KHQV Q 1 March. 2002 Rev 3.0 ...
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... K7P803666B K7P801866B IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform- ance with IEEE 1149 ...
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... K7P803666B K7P801866B SCAN REGISTER DEFINITION Part Instruction Register 256Kx36 3 bits 512Kx18 3 bits ID REGISTER DEFINITION Revision Number Part (31:28) 256Kx36 0000 512Kx18 0000 BOUNDARY SCAN EXIT ORDER(x36 ...
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... K7P803666B K7P801866B JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7P803666B K7P801866B 119 BGA PACKAGE DIMENSIONS 14.00 0.10 Indicator of Ball(1A) Location C1.00 0.60 0.10 12.50 0.10 119 BGA PACKAGE THERMAL CHARACTERISTICS Parameter Junction to Ambient(at still air) Junction to Case Junction to Board NOTE : 1. Junction temperature can be calculated 256Kx36 & 512Kx18 SRAM 22.00 0.10 20.50 0.10 C0.70 1.50REF NOTE : 0.60 0.10 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. ...