MACH435Q-25JC Lattice Semiconductor Corp., MACH435Q-25JC Datasheet
MACH435Q-25JC
Related parts for MACH435Q-25JC
MACH435Q-25JC Summary of contents
Page 1
FINAL MACH435-12/15/20, Q-20/25 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins in PLCC 128 Macrocells 12 ns tPD 83.3 MHz fCNT 70 Inputs with pull-up resistors 64 Outputs 192 Flip-flops — 128 Macrocell flip-flops — 64 Input flip-flops Up ...
Page 2
BLOCK DIAGRAM Clock Generator Clock Generator Clock Generator Clock Generator 2 I2, I5 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix ...
Page 3
CONNECTION DIAGRAM Top View I/O8 13 I/O9 14 I/O10 I/O11 15 I/O12 16 17 I/O13 18 I/O14 I/O15 19 20 CLK / GND 22 23 CLK / I/O16 24 I/O17 ...
Page 4
... Valid Combinations MACH435-12 MACH435-15 JC MACH435-20 MACH435Q-20 MACH435Q-25 4 MACH 435 - Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations ...
Page 5
FUNCTIONAL DESCRIPTION The MACH435 consists of eight PAL blocks connected by a central switch matrix. There are 64 I/O pins and 6 dedicated input pins feeding the central switch matrix. These signals are distributed to the eight PAL blocks for ...
Page 6
Table 1. Logic Allocation Macrocell Available Clusters M0 C0, C1 C0, C1, C2 C1, C2, C3 C2, C3, C4 C3, C4, C5 C4, C5, C6 C5, C6, C7, ...
Page 7
Input 24 Switch Matrix Figure 1. MACH435 PAL Block MACH435-12/15/20, Q-20/25 Clock Generator Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell M5 ...
Page 8
ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . Supply Voltage with Respect to Ground ...
Page 9
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) Parameter Symbol Parameter Description t Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback to Product Term Clock t Register Data Hold Time Using ...
Page 10
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued) Parameter Symbol Parameter Description t Input Register Clock to Output Register Setup ICS t WICL Input Register Clock Width t WICH f Maximum Input Register Frequency MAXIR t Input Latch Setup ...
Page 11
ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . Supply Voltage with Respect to Ground ...
Page 12
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note Setup Time from Input, I/O, or Feedback to Product Term Clock tHA Register Data Hold Time ...
Page 13
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued) Parameter Symbol Parameter Description t Input Register Clock to Output Register Setup ICS t WICL Input Register Clock Width t WICH f Maximum Input Register Frequency MAXIR t Input Latch Setup ...
Page 14
... 5 =25 MHz Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435Q-20 (Com’l) ) Operating + with +4. +5.25 V Min Typ = Min 2.4 2.0 – mA) 115 OUT = 25 C (Note 5) A Typ = 5 ...
Page 15
... Input Register Setup Time SIR t Input Register Hold Time HIR t Input Register Clock to Combinatorial Output ICO External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) MACH435Q-20 (Com’l) -20 Min Max Unit D-type 10 ns T-type ...
Page 16
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 16 D-type T-type LOW HIGH MACH435Q-20 (Com’l) -20 Min Max Unit ...
Page 17
... V = 5.0 V, OUT CC f=25 MHz (Note 5) A Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435Q-25 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 115 Typ = ...
Page 18
... SA COA T-type D-type ) CNTA T-type 1/( WLA WHA D-type T-type LOW HIGH D-type 1/( COS T-type D-type ) CNTS T-type 1/( MACH435Q-25 (Com’l) -25 Min Max Unit 21.7 MHz 21.3 MHz 24.4 MHz 23.8 MHz 26.3 MHz ...
Page 19
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. D-type T-type LOW HIGH 1/( WICL WICH MACH435Q-25 (Com’l) -25 Min Max Unit ...
Page 20
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS –1 (mA –0.8 –0.6 –0.4 –0 –20 –40 –60 –80 Output, LOW I (mA) OH ...
Page 21
... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH435Q Frequency (MHz) MACH435-12/15/20, Q-20/25 MACH435 50 60 ...
Page 22
TYPICAL THERMAL CHARACTERISTICS Measured ambient. These parameters are not tested. Parameter Symbol Parameter Description Thermal impedance, junction to case jc Thermal impedance, junction to ambient ja Thermal impedance, junction to ambient with air flow jma Plastic jc ...
Page 23
SWITCHING WAVEFORMS Input, I/O, or Combinatorial Input, I/O, or Feed- back t S Clock Registered Output Registered Output t WH Clock Clock Width Registered Input t SIR Input Register Clock Combinatorial Output Registered Input (MACH 2 and 4) Notes: 1. ...
Page 24
SWITCHING WAVEFORMS Latched In Gate Combinatorial Output Latched In Latched Out Input Latch Gate t IGS Output Latch Gate Notes 1 Input pulse amplitude 3 Input rise and fall ...
Page 25
SWITCHING WAVEFORMS t WICH Clock Input Register Clock Width (MACH 2 and 4) t ARW Input, I/O, or Feedback t AR Registered Output Clock Asynchronous Reset Input, I/O, or Feedback Notes 1 Input pulse ...
Page 26
KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUIT Specification Closed Open Closed Open Closed *Switching several outputs simultaneously should be avoided for ...
Page 27
ENDURANCE CHARACTERISTICS The MACH families are manufactured using our advanced Electrically Erasable process. This technol- ogy uses an EE cell to replace the fuse link used in Endurance Characteristics Parameter Symbol Parameter Description Min Pattern Data Retention Time t DR ...
Page 28
INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH435-12/15/20, Q-20/25 CC 100 17469E-24 29 ...
Page 29
POWER-UP RESET The MACH devices have been designed with the capa- bility to reset during system power-up. Following power- up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra ...
Page 30
USING PRELOAD AND OBSERVABILITY In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. In preload mode, each flip-flop in the MACH device can be loaded ...