W78E52B-24 Winbond, W78E52B-24 Datasheet
W78E52B-24
Available stocks
Related parts for W78E52B-24
W78E52B-24 Summary of contents
Page 1
... Three 16-bit timer/counters One full duplex serial port(UART) Watchdog Timer Eight sources, two-level interrupt capability EMI reduction mode Built-in power management Code protection mechanism Packages: DIP 40: W78E52B-24/40 PLCC 44: W78E52BP-24/40 PQFP 44: W78E52BF-24/40 Preliminary W78E52B 8-BIT MTP MICROCONTROLLER Publication Release Date: December 1998 - 1 - Revision A1 ...
Page 2
... ALE 12 29 INT0, P3.2 PSEN 13 28 P2.7, A15 INT1, P3.3 14 T0, P3.4 27 P2.6, A14 15 T1, P3.5 26 P2.5, A13 16 WR, P3.6 25 P2.4, A12 17 24 P2.3, A11 RD, P3 P2.2, A10 XTAL2 XTAL1 19 22 P2. VSS 21 P2.0, A8 44-Pin QFP (W78E52BF P1.5 P0.4, AD4 39 38 P1.6 P0.5, AD5 37 P1.7 P0.6, AD6 RST 36 P0.7, AD7 RXD, P3 ...
Page 3
... Timer 1 External Input WR (P3.6) : External Data Memory Write Strobe RD (P3.7) : External Data Memory Read Strobe P4.0-P4.3 PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O port or external interrupt input sources ( INT2 / INT3 ). Preliminary W78E52B DESCRIPTIONS Publication Release Date: December 1998 - 3 - Revision A1 ...
Page 4
... XTAL1 FUNCTIONAL DESCRIPTION The W78E52B architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space ...
Page 5
... External Interrupt 2 External Interrupt 3 IT3 PX2 EX2 POLLING SEQUENCE WITHIN PRIORITY LEVEL 03H 0 (highest) 0BH 1 13H 2 1BH 3 23H 4 2BH 5 33H 6 3BH 7 (lowest Preliminary W78E52B IE2 IT2 ENABLE INTERRUPT REQUIRED TYPE SETTINGS EDGE/LEVEL IE.0 TCON.0 IE.1 - IE.2 TCON.2 IE.3 - IE.4 - IE.5 - XICON.2 XICON.0 XICON.6 XICON.3 Publication Release Date: December 1998 ...
Page 6
... ROM code space. The AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation circuitry, W78E52B allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the B7 bit of security register. Once B7 is set half of gain will be decreased ...
Page 7
... PRESCALER 1000 12 mS OSC CLRW WIDL - Mnemonic: WDTC Address: 8FH PRESCALER SELECT 128 1 256 - 7 - Preliminary W78E52B has been applied to the part. It can PS2 PS1 Publication Release Date: December 1998 Revision A1 0 PS0 ...
Page 8
... Clock The W78E52B is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78E52B relatively insensitive to duty cycle variations in the clock. The W78E52B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground ...
Page 9
... The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E52B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. ...
Page 10
... Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The protection of MTP ROM and those operations on it are described below. The W78E52B has several Special Setting Registers, including the Security Register and Company/Device ID Registers, which can not be accessed in normal mode. These registers can only be accessed from the MTP-ROM operation mode ...
Page 11
... Default 1 for all security bits. Lock bit This bit is used to protect the customer's program code in the W78E52B. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the MTP ROM data and Special Setting Registers can not be accessed again. ...
Page 12
... 10 unless otherwise specified PARAMETER Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3 Logical 1-to-0 Transition (*1) Current P1, P2, P3 Input Current (*2) RST Preliminary W78E52B + PGM DATA EA/Vpp ALE ...
Page 13
... Pins P1, P2 and P3 source a transition current when they are being externally driven from The transition current reaches its maximum value when V is approximately 2V. IN *2. RST pin has an internal pull-down resistor. *3. P0, ALE, PSEN are in the external access memory mode. *4. XTAL1 is a CMOS input and RST is a Schmitt trigger input. Preliminary W78E52B SYMBOL TEST CONDITIONS 5. < ...
Page 14
... ALE Pulse Width PSEN Pulse Width Notes: 1. P0.0 P0.7, P2.0 P2.7 remain stable throughout entire memory cycle. 2. Memory access time Data have been latched internally prior to PSEN going high. 4. " " (due to buffer driving delay and wire loading nS. Preliminary W78E52B OP, CP SYMBOL MIN ...
Page 15
... Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. Program Operation PARAMETER V Setup Time PP Data Setup Time Data Hold Time Address Setup Time Address Hold Time Preliminary W78E52B SYMBOL MIN. TYP DAR CP T ...
Page 16
... OES T 0 DFP T - OEV ALW T APL T PSW T AAS T PDA T T PDH, PDZ A0-A7 A0-A7 Code A0-A7 Data - 16 - Preliminary W78E52B TYP. MAX. UNIT 300 310 130 nS - 150 nS status, the ALE pin must pull Data A0-A7 status, and ...
Page 17
... ALE PSEN PORT 2 PORT 0 A0- A8-A15 DATA T T DAR DDA T T DRD A8-A15 DATA OUT T DAD T T DWR DAW - 17 - Preliminary W78E52B DDH, DDZ DWD Publication Release Date: December 1998 Revision A1 ...
Page 18
... V IH (OE (A7... A0 Vcp Vpp VPS PDH Program Program Verify Address Stable T PWP OCS T OCH T OES T DFP T DH Data In D OUT T OEV - 18 - Preliminary W78E52B S1 T PDA DATA OUT Read Verify Address Valid Data Out ...
Page 19
... A11 P2.3 74373 25 A12 P2.4 26 A13 P2.5 27 A14 P2.6 28 A15 P2 PSEN 30 ALE 11 TXD 10 RXD Figure A C1 30P 30P 15P 15P 10P 10P Preliminary W78E52B ...
Page 20
... INT0 23 P2.2 A10 24 P2.3 A11 INT1 25 P2.4 A12 T0 P2.5 A13 26 T1 P2.6 A14 27 28 P2.7 P1 P1.3 29 PSEN P1.4 30 P1.5 ALE 11 P1.6 TXD 10 RXD P1.7 Figure Preliminary W78E52B ...
Page 21
... E Base Plane A 1 Seating Plane Preliminary W78E52B Dimension in inch Dimension in mm Symbol Min. Nom. Max. Min. Nom. 0.210 A 0.010 A 0.254 1 0.155 0.160 A 0.150 3.81 3.937 2 B 0.016 0.018 0.022 0.406 0.457 B 0 ...
Page 22
... Detail F 1 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 - 22 - Preliminary W78E52B Dimension in mm Dimension in inch Symbol Min. Nom. Max. Nom. Min. A --- --- --- --- --- A 0 ...